Electrostatic discharge protection device

1. A semiconductor electrostatic discharge protection device, comprising:

a semiconductor controlled rectifier; and

a p-n diode;

wherein the semiconductor controlled rectifier and the diode are integrally arranged laterally at a major surface of a semiconductor substrate; and wherein a current path for the semiconductor controlled rectifier is separate from a current path for the diode.

2. The semiconductor electrostatic discharge protection device of claim 1 , the semiconductor controlled rectifier comprising first and second transistors of opposite type, wherein:

a base and an emitter of the first transistor are arranged as a first input;

a base and emitter of the second transistor are arranged as a second input; and the diode is connected between the first and second inputs.

3. The semiconductor electrostatic discharge protection device of claim 2 , wherein the diode is arranged between the base of the first transistor and the base of the second transistor.

4. The semiconductor electrostatic discharge protection device of claim 1 ;

wherein the semiconductor controlled rectifier comprises a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type opposite to the first conductivity type; and wherein the p-n diode comprises the second semiconductor region and a third semiconductor region having a first conductivity type.

5. The semiconductor electrostatic discharge protection device of claim 4 , wherein first semiconductor region, second semiconductor region and third semiconductor region each comprise respective first and second doped regions of opposite conductivity type.

6. The semiconductor electrostatic discharge protection device of claim 5 , wherein the p-n diode comprises a first doped region of the third semiconductor region and a second doped region of the second semiconductor region.

7. The semiconductor electrostatic discharge protection device of claim 2 , wherein the respective first and second doped regions of the first semiconductor region and the respective first and third doped regions of the third semiconductor region comprise the first input, and the respective first and second doped regions of the second semiconductor region comprise the second input.

8. An array of semiconductor electrostatic discharge protection devices according to claim 1 , comprising an alternating array of semiconductor controlled rectifiers and diodes integrally laterally arranged on a substrate.

9. The array of semiconductor electrostatic discharge protection devices according to claim 8 , wherein the array comprises a lateral arrangement of first and second semiconductor regions of opposing conductivity.

10. The array of semiconductor electrostatic discharge protection devices according to claim 9 , wherein respective first and second doped regions of the first semiconductor regions form a first input terminal of the array, and the respective first and second doped regions of the second semiconductor regions form a second input terminal of the array.

11. The array of claim 1 , wherein the semiconductor controlled rectifiers further comprise low voltage trigger implants or diffusions.

12. A data transfer line comprising an electrostatic discharge protection device according to claim 1 or an array of electrostatic discharge protection devices.

13. A data interface comprising an electrostatic discharge protection device according to claim 1 or an array of electrostatic discharge protection devices, the array comprising an alternating array of semiconductor controlled rectifiers and diodes integrally laterally arranged on a substrate.