IP Library Granted Patent US 10,437,597
Granted Patent B2
US 10,437,597 · App. 14/848,498 · Granted Oct 8, 2019

Silent mode and resource reassignment in branch prediction logic

Inventors: James J. Bonanno (Wappingers Falls, NY); Adam B. Collura (Hopewell Junction, NY); Daniel Lipetz (Flushing, NY); Brian R. Prasky (Campbell Hall, NY); Anthony Saporito (Highland, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F9/3804G06F9/30058G06F9/30185G06F9/30189G06F9/3806G06F9/3842G06F9/3844G06F9/3851
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Quick Facts
Patent No.
US 10,437,597
App. No.
14/848,498
Granted
Oct 8, 2019
Kind
B2
Abstract

A method, system, and computer program product of utilizing branch prediction logic in a system that processes instructions that include a branch are described. The method includes identifying the branch as conventionally predictable or not conventionally predictable, and based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction and speculative execution of one or more of the instructions following the branch to obtain prediction information. Based on the performing the branch prediction and the speculative execution, the method also includes verifying a match between a branch end according to the instructions and a branch end according to the branch prediction prior to providing the prediction information to a second processor processing the instructions.

Claims (25)

1. A method of utilizing branch prediction logic in a system that processes instructions that include a branch, the method comprising:

identifying the branch as conventionally predictable or not conventionally predictable, wherein the branch is a not conventionally predictable branch when the branch is contained in a millicode routine;

based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating, using a processor, the branch prediction logic to another thread of the instructions or performing, using the processor, the branch prediction to determine a branch end of the branch and speculative execution of one or more of the instructions following the branch end to obtain a speculative execution result and store the speculative execution result in a queue;

based on the performing the branch prediction and the speculative execution, obtaining the speculative execution result from the queue and verifying a match between a branch end according to the instructions and the branch end according to the branch prediction prior to the processor providing the speculative execution result to a second processor processing the instructions, wherein the speculative execution result indicates data for the processor to prefetch;

the second processor prefetching the data in accordance with the speculative execution result based on the verifying the match and the providing the speculative execution result; and

updating a buffer associated with the branch prediction logic with the speculative execution result based on the verifying the match.

2. The method according to claim 1 , further comprising, based on the performing the branch prediction and the speculative execution, deleting the speculative execution result prior to providing the speculative execution result to the second processor based on verifying that the branch end according to the instructions and the branch end according to the branch prediction do not match.

3. The method according to claim 2 , further comprising instructing the second processor to proceed without the speculative execution result.

4. The method according to claim 1 , wherein the identifying is performed by the branch prediction logic.

5. The method according to claim 1 , wherein the identifying is done based on a marker generated by a compiler of the instructions.

6. A system for processing instructions that include a branch, the system comprising:

a processor configured to execute the instructions; and

branch prediction logic, configured for processing by a second processor, the branch prediction logic configured to identify the branch as a conventionally predictable branch or a not conventionally predictable branch and either forego branch prediction and reallocate the branch prediction logic to another thread of the instructions when the branch is the not conventionally predictable branch or perform the branch prediction to determine a branch end of the branch and speculative execution to generate a speculative execution result and store the speculative execution result in a queue when the branch is the not conventionally predictable branch, wherein when the branch prediction logic performs the branch prediction and the speculative execution when the branch is the not conventionally predictable branch, the processor obtains the speculative execution result from the queue and the branch prediction logic verifies a match between a branch end according to the instructions and the branch end according to the branch prediction prior to providing the speculative execution result to the processor processing the instructions, wherein the branch is a not conventionally predictable branch when the branch is contained in a millicode routine, the speculative execution result indicates data for the processor to prefetch and the processor prefetches the data based on verifying the match, and the branch prediction logic is further configured to update a buffer with the speculative execution result based on verifying the match.

7. The system according to claim 6 , wherein the branch prediction logic is further configured to identify the branch based on a marker generated by a compiler.

8. The system according to claim 6 , wherein the branch prediction logic is further configured to identify the branch according to the instructions.

9. A computer program product for performing branch prediction logic, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to perform a method comprising:

identifying the branch as conventionally predictable or not conventionally predictable, wherein the branch is a not conventionally predictable branch when the branch is contained in a millicode routine;

based on the branch being identified as not conventionally predictable according to the identifying, either foregoing branch prediction and reallocating the branch prediction logic to another thread of the instructions or performing the branch prediction to determine a branch end of the branch and speculative execution of one or more of the instructions following the branch to obtain a speculative execution result and store the speculative execution result in a queue;

based on the performing the branch prediction and the speculative execution, obtaining the speculative execution result from the queue and verifying a match between a branch end according to the instructions and the branch end according to the branch prediction prior to providing the speculative execution result to a second processor processing the instructions, wherein the speculative execution result indicates data for the processor to prefetch;

the second processor prefetching the data in accordance with the speculative execution result based on the verifying the match and the providing the speculative execution result; and

updating a buffer associated with the branch prediction logic with the speculative execution result based on the verifying the match.

10. The computer program product according to claim 9 , further comprising, based on the performing the branch prediction and the speculative execution, deleting the speculative execution result prior to providing the speculative execution result to the second processor based on verifying that the branch end according to the instructions and the branch end according to the branch prediction do not match.

11. The computer program product according to claim 10 , further comprising instructing the second processor to proceed without the speculative execution result.

12. The computer program product according to claim 9 , wherein the identifying is done by the branch prediction logic.

13. The computer program product according to claim 9 , wherein the identifying is done based on a marker generated by a compiler of the instructions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2015
From: BONANNO, JAMES J.; COLLURA, ADAM B.; LIPETZ, DANIEL; PRASKY, BRIAN R.; SAPORITO, ANTHONY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 036518/0001 →
Continuity (1)
Related Publication 20170068538A1 · Mar 9, 2017