IP Library Granted Patent US 9,379,035
Granted Patent B1
US 9,379,035 · App. 14/850,966 · Granted Jun 28, 2016

IC package having non-horizontal die pad and lead frame therefor

Inventors: You Ge (Tianjin, CN); Meng Kong Lye (Shah Alam, MY); Zhijie Wang (Tianjin, CN)
Assignee: FREESCALE SEMICONDUCTOR, INC.
H01L23/367H01L21/56H01L23/053H01L23/49541H01L23/49568H01L23/49575H01L24/49H01L24/85H01L25/065H01L2924/15158
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Quick Facts
Patent No.
US 9,379,035
App. No.
14/850,966
Granted
Jun 28, 2016
Kind
B1
Abstract

A multi-component integrated circuit (IC) package has a base component (e.g., an interposer) defining a base of the IC package, a plurality of die pads extending from the base and forming side walls of the IC package, one or more IC dies, each mounted on an interior surface of one of the die pads, and bond wires electrically connecting the IC dies to another component of the IC package, such as the interposer or another die. By mounting dies on non-horizontal side walls, the IC package can provide more-effective thermal dissipation than conventional 3D IC packages having stacks of IC dies.

Claims (39)

1. A multi-component integrated circuit (IC) package comprising:

a base component defining a base of the IC package;

a plurality of die pads extending from the base and forming side walls of the IC package;

one or more IC dies, each mounted on an interior surface of one of the die pads; and

a plurality of wires, each wire connecting a corresponding IC die to another component of the IC package, and

wherein the base component is an interposer, and at least one wire connects a corresponding IC die to the interposer.

2. The IC package of claim 1 , wherein a bottom surface of the interposer has at least one solder ball electrically connected to the at least one wire by a through-silicon via in the interposer.

3. The IC package of claim 1 , comprising four vertical die pads forming four side walls of the IC package, wherein a space defined by the base component and the four vertical die pads is at least partially filled with an encapsulant that encapsulates the wires.

4. The IC package of claim 1 , wherein the wires comprise an insulated bond wires connected to bond pads on the base component and a corresponding IC die.

5. The IC package of claim 1 , wherein the wires comprise an insulated nanotube connected to wafer-level bumps on the base component and a corresponding IC die.

6. The IC package of claim 1 , further comprising an encapsulant that covers the wires.

7. The IC package of claim 6 , further comprising a cap forming a top side of the IC package.

8. The IC package of claim 7 , wherein the cap has a central post extending into the encapsulant such that the encapsulant secures the cap onto the IC package.

9. A lead frame for an IC package, the lead frame comprising a plurality of die pads surrounding a central opening and pivotally connected at pivotal connections such that each die pad can receive an IC die and be rotated about the pivotal connections relative to the central opening to define a side wall of the IC package having the mounted IC die.

10. The lead frame of claim 9 , wherein the lead frame is mounted on adhesive tape, such that the adhesive tape located at the central opening can receive an interposer to be electrically connected to at least one mounted IC die by one or more wires.

11. The lead frame of claim 9 , comprising four die pads located on four sides of a rectangular central opening and pivotally connected such that each die pad can receive a corresponding IC die and be rotated to a vertical orientation relative to the central opening to define a vertical side wall of the IC package having the mounted IC die, wherein the four vertical die pads define the four vertical side walls of a rectilinear IC package.

12. The lead frame of claim 11 , further comprising four diagonal tie bars supporting the four die pads at eight pivotal connections, wherein the four diagonal tie bars connect the lead frame to one or more adjacent lead frames in a lead frame array.

13. The lead frame of claim 12 , wherein the pivotal connections are configured to break when the die pads are rotated to the vertical orientations.

14. A method for assembling an IC package, the method comprising:

(a) mounting a base component onto adhesive tape located at the central opening of a lead frame having a plurality of die pads surrounding the central opening;

(b) mounting one or more IC dies onto one or more of the die pads;

(c) connecting wires between the base component and each mounted IC die;

(d) rotating each die pad relative to the base component to form a side wall of the IC package; and

(e) applying encapsulant to encapsulate the wires.

15. The method of claim 14 , wherein:

the central opening is rectangular;

the lead frame has four die pads located on the four sides of a rectangular central opening;

step (b) comprises mounting the one or more IC dies onto the four die pads; and

step (d) comprises rotating the four die pads with the one or more connected, mounted IC dies to form four vertical side walls of the IC package.

16. The method of claim 15 , further comprising:

applying a cap over the four side walls to form a top side of the IC package, wherein:

the cap has a post extending into the interior of the IC package;

the cap is applied before the encapsulant is fully cured; and

the encapsulant is fully cured to anchor the post within the cured encapsulant to secure the cap onto the IC package.

17. The method of claim 14 , wherein:

the lead frame has tie bars supporting the die pads at bar/pad interconnections; and

the bar/pad interconnections break when the die pads are rotated relative to the base component.

18. The method of claim 14 , wherein the base component is an interposer.

19. An IC package assembled using the method of claim 14 .

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2015
From: GE, YOU; WANG, ZHIJIE; LYE, MENG KONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 036548/0809 →
Priority Claims (1)
CN 2015 1 0139788 · Feb 26, 2015 · national