IP Library Granted Patent US 9,533,880
Granted Patent B2
US 9,533,880 · App. 14/853,873 · Granted Jan 3, 2017

Method of fabrication of Al/Ge bonding in a wafer packaging environment and a product produced therefrom

Inventors: Steven S. Nasiri (Saratoga, CA); Anthony F. Flannery, Jr. (Los Gatos, CA)
Assignee: INVENSENSE, INC.
B81C1/00269B23K20/023B81B3/0018B81C1/00238B81C3/001H01L21/187B81C2203/0118B81C2203/035B81C2203/038
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Quick Facts
Patent No.
US 9,533,880
App. No.
14/853,873
Granted
Jan 3, 2017
Kind
B2
Abstract

A method of bonding of germanium to aluminum between two substrates to create a robust electrical and mechanical contact is disclosed. An aluminum-germanium bond has the following unique combination of attributes: (1) it can form a hermetic seal; (2) it can be used to create an electrically conductive path between two substrates; (3) it can be patterned so that this conduction path is localized; (4) the bond can be made with the aluminum that is available as standard foundry CMOS process. This has the significant advantage of allowing for wafer-level bonding or packaging without the addition of any additional process layers to the CMOS wafer.

Claims (18)

1. A method for bonding a first substrate wafer and a second substrate wafer by creating an aluminum/germanium bond, a patterned aluminum layer disposed on the first substrate wafer, a patterned germanium layer disposed on the second substrate wafer, the method comprising:

placing the first substrate wafer in a first chuck; placing the second substrate wafer in a second chuck; aligning the first substrate wafer and the second substrate wafer; and forming a eutectic bond between the patterned germanium layer and the patterned aluminum layer, wherein the eutectic bond is formed by applying a force across the first chuck and the second chuck, and ramping temperature of at least one of the first chuck or the second chuck over a eutectic temperature of the aluminum/germanium bond to a predetermined temperature that is between the eutectic temperature of the aluminum/germanium bond and 450 degrees Celsius (C.).

2. The method of claim 1 , wherein one of the first substrate wafer and the second substrate wafer is a cover wafer.

3. The method of claim 1 , further comprising:

providing an insulating layer between the second substrate wafer and a portion of the patterned germanium layer.

4. A method for bonding a first substrate wafer and a second substrate wafer by creating an aluminum/germanium bond, an aluminum layer disposed on the first substrate wafer, a germanium layer disposed on the second substrate wafer, the method comprising:

placing the first substrate wafer in a first chuck;

placing the second substrate wafer in a second chuck;

aligning the first substrate wafer and the second substrate wafer; and

forming a eutectic bond between the germanium layer and the aluminum layer, wherein the eutectic bond is formed by applying a force across the first chuck and the second chuck, and ramping temperature of at least one of the first chuck or the second chuck over a eutectic temperature of the aluminum/germanium bond.

5. The method of claim 4 , wherein the ramping of the temperature includes ramping the temperature greater than the eutectic temperature and not exceeding 450 degrees Celsius (C.).

6. The method of claim 4 , wherein one of the first substrate wafer and the second substrate wafer is a cover wafer.

7. The method of claim 4 , wherein the placing the second substrate wafer in the second chuck includes placing the second substrate wafer comprising a microelectromechanical systems (MEMS) structure in the second chuck.

8. The method of claim 7 , wherein the placing the first substrate wafer in the first chuck includes placing the first substrate wafer comprising a complementary metal-oxide semiconductor (CMOS) structure in the first chuck.

9. The method of claim 8 , wherein the forming the eutectic bond comprises creating, with the aluminum/germanium bond, at least one of at least one electrical connection or a hermetic seal between first substrate wafer and the second substrate wafer, wherein the hermetic seal forms a partial enclosure of the MEMS structure.

10. The method of claim 1 , wherein the placing the second substrate wafer in the second chuck includes placing the second substrate wafer comprising a microelectromechanical systems (MEMS) structure in the second chuck.

11. The method of claim 1 , wherein the placing the first substrate wafer in the first chuck includes placing the first substrate wafer comprising a complementary metal-oxide semiconductor (CMOS) substrate in the first chuck.

12. The method of claim 4 , wherein the forming the eutectic bond comprises creating, with the aluminum/germanium bond, at least one of at least one electrical connection or a hermetic seal between first substrate wafer and the second substrate wafer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2015
From: NASIRI, STEVEN S.; FLANNERY, JR., ANTHONY F.
To: INVENSENSE, INC.
Reel/Frame 036561/0236 →
Continuity (5)
Continuation 14157456 · Jan 16, 2014
Continuation 13333580 · Dec 21, 2011
Continuation 12184231 · Jul 31, 2008
Continuation 11084296 · Mar 18, 2005
Related Publication 20160002029A1 · Jan 7, 2016