Power converter package with integrated output inductor
View Patent ↗In one implementation, a semiconductor package includes a first patterned conductive carrier including partially etched segments. The semiconductor package also includes a control FET having a control drain attached to a first partially etched segment of the first patterned conductive carrier. In addition, the semiconductor package includes a sync FET having a sync source and a sync gate attached to respective second and third partially etched segments of the first patterned conductive carrier. The semiconductor package further includes a second patterned conductive carrier having a switch node segment situated over a control source of the control FET and over a sync drain of the sync FET, as well as an inductor coupled between the switch node segment and an output segment of the second patterned conductive carrier.
1. A semiconductor package comprising:
a first patterned conductive carrier;
a control field-effect transistor (FET) having a control drain attached to a first partially etched segment of said first patterned conductive carrier;
a synchronous (sync) FET having a sync source and a sync gate attached to respective second and third partially etched segments of said first patterned conductive carrier;
a second patterned conductive carrier having a switch node segment situated over a control source of said control FET and over a sync drain of said sync FET; and
an inductor coupled between said switch node segment and an output segment of said second patterned conductive carrier.
2. The semiconductor package of claim 1 , wherein said first, second, and third partially etched segments of said first patterned conductive carrier are substantially half-etched.
3. The semiconductor package of claim 1 , wherein said switch node segment of said second patterned conductive carrier is partially etched.
4. The semiconductor package of claim 1 , wherein said control FET, said sync FET, and said inductor form an output stage of a power converter.
5. The semiconductor package of claim 1 , wherein at least one of said first patterned conductive carrier and said second patterned conductive carrier comprises at least a portion of a lead frame.
6. The semiconductor package of claim 1 , wherein said second patterned conductive carrier comprises at least a portion of a lead frame.
7. The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise silicon power FETs.
8. The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise group III-Nitride FETs.
9. The semiconductor package of claim 1 , wherein said control FET and said sync FET comprise group III-Nitride high electron mobility transistors (HEMTs).
10. The semiconductor package of claim 1 , further comprising a driver integrated circuit for driving at least one of said control FET and said sync FET.
11. A semiconductor package comprising:
a first patterned conductive carrier;
a control field-effect transistor (FET) having a control drain attached to a first partially etched segment of said first patterned conductive carrier;
a synchronous (sync) FET having a sync source and a sync gate;
a second patterned conductive carrier having a switch node segment situated over a control source of said control FET and over a sync drain of said sync FET; and
an inductor coupled between said switch node segment and an output segment of said second patterned conductive carrier.
12. The semiconductor package of claim 11 , wherein said switch node segment of said second patterned conductive carrier is partially etched.
13. The semiconductor package of claim 11 , wherein said control FET, said sync FET, and said inductor form an output stage of a power converter.
14. The semiconductor package of claim 11 , wherein at least one of said first patterned conductive carrier and said second patterned conductive carrier comprises at least a portion of a lead frame.
15. The semiconductor package of claim 11 , wherein said second patterned conductive carrier comprises at least a portion of a lead frame.
16. The semiconductor package of claim 11 , wherein said control FET and said sync FET comprise silicon power FETs.
17. The semiconductor package of claim 11 , wherein said control FET and said sync FET comprise group III-Nitride FETs.
18. The semiconductor package of claim 11 , wherein said control FET and said sync FET comprise group III-Nitride high electron mobility transistors (HEMTs).
19. The semiconductor package of claim 11 , further comprising a driver integrated circuit for driving at least one of said control FET and said sync FET.