Fully silicided linerless middle-of-line (MOL) contact
A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide.
1. A semiconductor device, comprising:
a substrate;
a gate disposed over the substrate, the gate comprising a hard mask cap arranged on a top surface of the gate;
a spacer arranged directly on a lateral sidewall of the gate and directly on a lateral sidewall of the hard mask cap, the spacer being partially recessed with respect to the hard mask cap such that the spacer is arranged only on a portion of the lateral sidewall of the hard mask cap, leaving another portion of the lateral sidewall of the hard mask cap being exposed;
a source/drain region disposed over the substrate and adjacent to the spacer; and
a silicide contact formed over the source/drain region, a silicide of the silicide contact arranged in direct contact with the source/drain region and over and in direct contact with a recessed portion of the spacer such that the silicide also directly contacts exposed lateral side and a top surface of the hard mask cap.
2. The semiconductor device of claim 1 , wherein the hard mask cap has a thickness in a range from about 20 to about 30 nm.
3. The semiconductor device of claim 1 , wherein the silicide contact comprises a first portion adjacent to the spacer and a second portion over the spacer, the first portion having a width that is less than the second portion.
4. The semiconductor device of claim 1 , wherein the silicide contact comprises nickel silicide.
5. The semiconductor device of claim 1 , wherein the silicide comprises a refractory metal.
6. The semiconductor device of claim 1 , wherein the source/drain region comprises silicon, silicon germanium, or a combination thereof.
7. A semiconductor device, comprising:
a substrate;
a first gate disposed over the substrate, the first gate comprising a first hard mask cap arranged on a top surface of the first gate;
a first spacer arranged directly on a lateral sidewall of the first gate and directly on a lateral sidewall of the first hard mask cap, the first spacer being partially recessed with respect to the first hard mask cap such that the first spacer is arranged only on a portion of the lateral sidewall of the first hard mask cap, leaving another portion of the lateral sidewall of the first hard mask cap being exposed;
a second gate disposed over the substrate adjacent to the first gate, the second gate comprising a second hard mask cap arranged on a top surface of the second gate;
a second spacer arranged directly on a lateral sidewall of the second gate and directly on a lateral sidewall of the second hard mask cap, the second spacer being partially recessed with respect to the second hard mask cap such that the second spacer is arranged only on a portion of the lateral sidewall of the second hard mask cap, leaving another portion of the lateral sidewall of the second hard mask cap being exposed;
a source/drain region arranged on the substrate between the first gate and the second gate; and
a silicide contact formed over the source/drain region, a silicide of the silicide contact arranged in direct contact with the source/drain region, and over and in direct contact with recessed portions of the first spacer and the second spacer such that the silicide directly contacts exposed lateral sidewalls and top surfaces of the first hard mask cap and the second hard mask cap.