High voltage architecture for non-volatile memory

1. A system, comprising:

a non-volatile memory (NVM) cell coupled to a common source line (CSL), wherein the CSL is shared among the NVM cell of a first row of NVM cells and one or more other NVM cells of the first row of NVM cells in a direction of the first row;

a local bit line (BL) coupled to the NVM cell;

a word line (WL) coupled to the NVM cell; and

a voltage control circuit to control a plurality of high voltage (HV) signals for operation of the NVM cell while maintaining a safe operating area (SOA), wherein the plurality of HV signals are above a highest voltage of a power supply of a memory device or below a lowest voltage of a ground supply, the voltage control circuit to apply:

a first HV signal (VPOS) to the CSL and BL during an erase operation to erase the NVM cell, wherein the first HV signal is above the highest voltage of the power supply; and

a second high voltage (HV) signal (VNEG) to the WL and to a substrate line (SPW) during a program operation to program the NVM cell, wherein the second HV signal is below the lowest voltage of the ground supply of the memory device.

2. The system of claim 1 , further comprising:

a sector select circuit, coupled to a column of NVM cells of the sector, to control a bit line voltage applied of a local bit line (BL), the sector select circuit comprising three metal oxide semiconductor field-effect transistors (MOSFET).

3. The system of claim 2 , wherein the sector select circuit comprises:

a first N-channel metal oxide semiconductor field-effect transistor (nMOSFET) comprising a first gate, a first well, a first source, and first drain coupled to the BL;

a second nMOSFET comprising a second gate, a second well, a second drain, and second source coupled to the BL; and

a P-channel metal oxide semiconductor field-effect transistor (pMOSFET) comprising a third gate, a third well, a third drain, and third source coupled to the BL.

4. The system of claim 1 , wherein the SOA is a set of voltage differentials between different terminals of a transistor within which the transistor may be biased without damaging the transistor.

5. An apparatus, comprising:

a non-volatile memory (NVM) cell of first row of NVM cells of a memory device;

a common source line (CSL) coupled to the NVM cell, wherein the CSL is shared among the NVM cell and one or more other NVM cells of the first row of NVM cells in a direction of the first row;

a local bit line (BL) coupled to the NVM cell;

a second word line (WL) coupled to the NVM cell;

a substrate line (SPW) coupled to the NVM cell; and

a voltage control circuit to apply a first high voltage (HV) signal (VPOS) to the CSL and the BL to erase the NVM cell during an erase operation, wherein the first HV signal is above a highest voltage of a power supply of the memory device, and to apply a second HV signal (VNEG) to the WL and to the SPW and a third HV signal (VNEG 3 ) to the CSL to program the NVM cell during a program operation.

6. The apparatus of claim 5 , further comprising:

a first word line (WLS) coupled to the NVM cell;

a substrate line (SPW) coupled to the NVM cell; and

the voltage control circuit to apply the first HV signal to the substrate line (SPW) and to apply a second HV signal (VNEG) to the WLS to erase the NVM cell during an erase operation, wherein the second HV signal is below a lowest voltage of a ground supply of the memory device.

7. The apparatus of claim 5 , further comprising

a second word line (WL) coupled to the NVM cell; and

the voltage control circuit to apply a fourth HV signal (VBST) to the WL to read the NVM cell during a read operation, wherein the fourth HV signal is above the highest voltage of the power supply.

8. The apparatus of claim 5 , wherein the NVM cell is a charge trapping memory cell.

9. The apparatus of claim 5 , wherein the CSL is shared between a plurality of rows of NVM cells and a plurality of columns of NVM cells of the NVM sector.