IP Library › Granted Patent US 9,748,291
Granted Patent B2
US 9,748,291 · App. 14/859,530 · Granted Aug 29, 2017

Imaging device having a third circuit with a region overlapping with a fourth circuit

Inventors: Takayuki Ikeda (Kanagawa, JP); Yoshiyuki Kurokawa (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/14612H01L27/14634H01L27/14645H01L27/14659H01L27/14663H01L29/24H01L29/7869H01L31/0272H01L31/0322H01L27/14621H01L27/14627
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Quick Facts
Patent No.
US 9,748,291
App. No.
14/859,530
Granted
Aug 29, 2017
Kind
B2
Abstract

An imaging device which offers an image with high quality and is suitable for high-speed operation is provided. The imaging device includes a first region to an n-th region (n is a natural number of 2 or more and 16 or less) each including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first to third circuits each include a transistor in which silicon is used in an active layer or an active region. The fourth circuit includes a photoelectric conversion element and a transistor in which an oxide semiconductor is used in an active layer. The first circuit includes a region overlapping with the fourth circuit. The third circuit includes a region overlapping with the fourth circuit.

Claims (50)

1. An imaging device comprising:

a first region to an n-th region (n is a natural number of 2 or more and 16 or less); and

a first circuit, a second circuit, a third circuit, and a fourth circuit in each of the first region to the n-th region,

wherein the first to third circuits each include a transistor including silicon in a channel formation region,

wherein the fourth circuit includes a photoelectric conversion element and a transistor including an oxide semiconductor in a channel formation region,

wherein the first circuit is configured to read out a first signal from the third circuit,

wherein the second circuit is configured to output a second signal for driving the fourth circuit,

wherein the third circuit is configured to process a third signal output from the fourth circuit,

wherein the fourth circuit is configured to convert light into the third signal,

wherein the first circuit includes a region overlapping with the fourth circuit, and

wherein the third circuit includes a region overlapping with the fourth circuit.

2. The imaging device according to claim 1 , wherein the oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

3. The imaging device according to claim 1 , wherein the photoelectric conversion element includes selenium.

4. The imaging device according to claim 1 , wherein the first circuit and the second circuit each include a shift register circuit and a buffer circuit.

5. The imaging device according to claim 1 , wherein the third circuit includes a correlated double sampling circuit, an analog-to-digital converter circuit, and a latch circuit.

6. The imaging device according to claim 1 , wherein the first circuit is divided and positioned in two regions.

7. The imaging device according to claim 1 , wherein the second circuit is divided and positioned in two regions.

8. The imaging device according to claim 1 ,

wherein the first circuit, the second circuit, and the third circuit are in a first layer,

wherein the transistor included in the fourth circuit is in a second layer,

wherein the photoelectric conversion element is in a third layer, and

wherein the second layer is between the first layer and the third layer.

9. An electronic device comprising:

the imaging device according to claim 1 ; and

a display device.

10. An imaging device comprising a pixel portion, the imaging device comprising:

a first circuit, a second circuit, a third circuit, and a fourth circuit,

wherein the first to third circuits each include a transistor including silicon in a channel formation region,

wherein the pixel portion includes the fourth circuit,

wherein the fourth circuit includes a photoelectric conversion element and a transistor including an oxide semiconductor in a channel formation region,

wherein the first circuit is configured to read out a first signal from the third circuit,

wherein the second circuit is configured to output a second signal for driving the fourth circuit,

wherein the third circuit is configured to process a third signal output from the fourth circuit,

wherein the fourth circuit is configured to convert light into the third signal,

wherein the first circuit includes a region overlapping with the pixel portion, and

wherein the third circuit includes a region overlapping with the pixel portion.

11. The imaging device according to claim 10 , wherein the oxide semiconductor includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

12. The imaging device according to claim 10 , wherein the photoelectric conversion element includes selenium.

13. The imaging device according to claim 10 , wherein the first circuit and the second circuit each include a shift register circuit and a buffer circuit.

14. The imaging device according to claim 10 , wherein the third circuit includes a correlated double sampling circuit, an analog-to-digital converter circuit, and a latch circuit.

15. The imaging device according to claim 10 , wherein the first circuit is divided and positioned in two regions.

16. The imaging device according to claim 10 , wherein the second circuit is divided and positioned in two regions.

17. The imaging device according to claim 10 ,

wherein the first circuit, the second circuit, and the third circuit are in a first layer,

wherein the transistor included in the fourth circuit is in a second layer,

wherein the photoelectric conversion element is in a third layer, and

wherein the second layer is between the first layer and the third layer.

18. An electronic device comprising:

the imaging device according to claim 10 ; and

a display device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2015
From: IKEDA, TAKAYUKI; KUROKAWA, YOSHIYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 036654/0824 →
Priority Claims (1)
JP 2014-196247 · Sep 26, 2014 · national
Continuity (1)
Related Publication 20160093652A1 · Mar 31, 2016