Method and apparatus for a high resolution imaging system

1. An imaging apparatus comprising:

a first apparatus comprising a first substrate with a multitude of imaging elements arrayed thereupon, wherein the imaging elements are capable of emitting an imaging signal from their structure to a material sensitive to their emissions on a surface in a vicinity of the first apparatus, wherein the imaging elements are emission tips formed into silicon deposited into trenches, and wherein the emission tips protrude from a backside of a base layer into a front-side of which the trenches are etched, and wherein there are more than 1000 emission tips in the first apparatus;

a support component for a second substrate to be processed by the imaging apparatus;

an alignment feature and alignment apparatus to measure the alignment feature; and

a processor operant to collect data from imaging apparatus components, process the data and control imaging apparatus components based on the data.

2. The imaging apparatus of claim 1 further comprising a cooling device in thermal communication with the second substrate.

3. The imaging apparatus of claim 1 further comprising a piezoelectric actuating device to raster the imaging apparatus.

4. The imaging apparatus of claim 3 wherein the rastering comprises at least ten steps within a distance separating two of the emission tips.

5. A method of forming an imaging system comprising:

forming two or more individual imaging system elements, the method of forming the elements comprising:

etching a plurality of trenches into a base layer;

partially filing the trenches with conformal dielectric films;

filling the trenches with polysilicon;

finishing processing of an integrated circuit with metal layers;

processing the integrated circuit to thin a backside of the base layer, wherein the thinning exposes a dielectric film of one or more dielectric films which coat the polysilicon;

removing the one or more dielectric films to reveal polysilicon filaments;

etching the polysilicon filaments to form tips;

testing two or more of the individual imaging system elements;

selecting two or more of the individual imaging system elements based on compliance to desired specifications;

forming a receiving substrate with electrical interconnect features thereon;

placing two or more selected individual imaging system elements upon the receiving substrate; and

electrically connecting two or more individual imaging elements to electrically connect them upon the receiving substrate.

6. The method of claim 5 additionally comprising:

testing the imaging system to form test structures;

measuring the test structures; and

calculating correction values utilizing result of the measuring.

7. The method of claim 5 wherein the imaging system comprises more than 10,000,000 individual imaging elements.

8. The method of claim 7 wherein the imaging system is approximately round in form with a radius of approximately 1 inch.

9. The method of claim 8 additionally comprising the step of:

including the imaging elements into a toolPod.

10. The method of claim 9 additionally comprising steps of:

placing the toolPod upon a chassis, wherein the chassis is part of a cleanspace fabricator;

placing a second substrate into the cleanspace fabricator;

placing an imaging sensitive film upon the second substrate; and

performing an imaging process upon the imaging sensitive film upon the second substrate.

11. An imaging apparatus comprising:

an array of emission tips, wherein the emission tips comprise polysilicon formed into cavities in a base layer, wherein the emission tips are sharpened by an etching process;

a dielectric layer surrounding the emission tips at least in a portion of the emission tips that is surrounded by the base layer; and

electrical circuits connected to each of the emission tips, wherein the electrical circuits bias the tips based on data related to an image.

12. The imaging apparatus of claim 11 wherein the electrical circuits that bias the tips are fabricated in a high voltage CMOS processing flow.

13. The imaging apparatus of claim 12 wherein a bias potential that the electrical circuits bias the tips to exceeds 5 volts.

14. The imaging apparatus of claim 13 wherein the bias potential that the electrical circuits bias the tips to exceeds 25 volts.

15. The imaging apparatus of claim 11 wherein a prefabricated embedded dram memory device is further processed to expose the array of emission tips.