Hardware predictor using a cache line demotion instruction to reduce performance inversion in core-to-core data transfers

1. An apparatus comprising:

a plurality of hardware processor cores, wherein each of the hardware processor cores includes a first cache;

a second cache, communicatively coupled to and shared by the plurality of hardware processor cores; and

a predictor circuit for tracking accesses to a plurality of monitored cache lines in the first cache and controlling enablement of a cache line demotion instruction based upon the tracked accesses, wherein the predictor circuit is operable to:

store addresses of a plurality of cache lines in the first cache;

maintain a counter for tracking a number of intra-core accesses compared to a number of inter-core accesses;

increment the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache;

decrement the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache;

disable the cache line demotion instruction upon the counter exceeding a first threshold; and

enable the cache line demotion instruction upon the counter dropping below a second threshold;

wherein an execution of the cache line demotion instruction by one of the plurality of hardware processor cores causes a plurality of unmonitored cache lines in the first cache to be moved to the second cache.

2. The apparatus of claim 1 , wherein the first cache is a level 1 cache and the second cache is a level 2 cache.

3. The apparatus of claim 1 , wherein the first cache is a mid-level cache and the second cache is a last-level cache.

4. The apparatus of claim 1 , wherein the inter-core accesses comprise snoop requests.

5. The apparatus of claim 1 , wherein each of the plurality of hardware processor cores includes a decoder to decode the cache line demotion instruction and execution hardware to execute a decoded cache line demotion instruction to move a cache line from the first cache to the second cache.

6. The apparatus of claim 1 , wherein the plurality of monitored cache lines in the first cache are randomly selected.

7. A method implemented in a hardware processor, the method comprising:

tracking accesses to a plurality of monitored cache lines in a first cache of the hardware processor; and

controlling enablement of a cache line demotion instruction based on the tracked accesses;

wherein the tracking and controlling further comprises:

storing addresses of a plurality of cache lines in the first cache;

maintaining a counter for tracking a number of intra-core accesses compared to a number of inter-core accesses;

incrementing the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache;

decrementing the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache;

disabling the cache line demotion instruction upon the counter exceeding a first threshold; and

enabling the cache line demotion instruction upon the counter dropping below a second threshold;

wherein an execution of the cache line demotion instruction causes a plurality of unmonitored cache lines in the first cache to be moved to a second cache of the hardware processor.

8. The method of claim 7 , further comprising:

decoding the cache line demotion instruction;

executing a decoded cache line demotion instruction; and

moving a cache line from the first cache to the second cache.

9. The method of claim 7 , further comprising:

randomly selecting the plurality of monitored cache lines in the first cache.

10. An apparatus comprising:

a plurality of hardware processor cores, wherein each of the hardware processor cores includes a first cache;

a second cache, communicatively coupled to and shared by the plurality of hardware processor cores; and

a predictor circuit for tracking accesses to a plurality of monitored cache lines in the first cache and controlling enablement of a cache line demotion instruction based upon the tracked accesses, wherein the predictor circuit is operable to:

store addresses of a plurality of cache lines in the first cache;

maintain a counter for tracking a number of intra-core accesses compared to a number of inter-core accesses;

decrement the counter upon an intra-core access to an address of one of the plurality of monitored cache lines in the first cache;

increment the counter upon an inter-core access to an address of one of the plurality of monitored cache lines in the first cache;

enable the cache line demotion instruction upon the counter exceeding a first threshold; and

disable the cache line demotion instruction upon the counter dropping below a second threshold;

wherein an execution of the cache line demotion instruction by one of the plurality of hardware processor cores causes a plurality of unmonitored cache lines in the first cache to be moved to the second cache.

11. The apparatus of claim 10 , wherein the first cache is a level 1 cache and the second cache is a level 2 cache.

12. The apparatus of claim 10 , wherein the first cache is a mid-level cache and the second cache is a last-level cache.

13. The apparatus of claim 10 , wherein the inter-core accesses comprise snoop requests.

14. The apparatus of claim 10 , wherein each of the plurality of hardware processor cores includes a decoder to decode the cache line demotion instruction and execution hardware to execute a decoded cache line demotion instruction to move a cache line from the first cache to the second cache.

15. The apparatus of claim 10 , wherein the plurality of monitored cache lines in the first cache are randomly selected.