System with cache-coherent memory and server-linking switch
A system and method for managing memory resources. In some embodiments the system includes a first server, a second server, and a server-linking switch connected to the first server and to the second server. The first server may include a stored-program processing circuit, a cache-coherent switch, and a first memory module. In some embodiments, the first memory module is connected to the cache-coherent switch, the cache-coherent switch is connected to the server-linking switch, and the stored-program processing circuit is connected to the cache-coherent switch.
1 . A system, comprising:
a first computing device, comprising:
a first switch including a processing device configured to adhere to a cache coherent protocol;
a first memory device and a second memory device connected to the first switch, wherein the first memory device is associated with a first memory technology and the second memory device is associated with a second memory technology different from the first memory technology; and
a second switch connected to the first computing device,
wherein:
the second switch is configured to receive a first data request and a second data request, wherein the first data request and the second data request adhere to the cache coherent protocol,
the processing device of the first switch is configured to:
identify the first memory device based on the first data request;
translate the first data request into a third data request based on the first memory technology, wherein the third data request adheres to a first memory protocol different from the cache coherent protocol;
transmit the third data request to the first memory device for accessing the first memory device;
identify the second memory device based on the second data request;
translate the second data request to a fourth data request based on the second memory technology, wherein the fourth data request adheres to a second memory protocol different from the first memory protocol and the cache coherent protocol; and
transmit the fourth data request to the second memory device for accessing the second memory device.
2 . The system of claim 1 , wherein the second switch is configured based on a storage protocol.
3 . The system of claim 1 , wherein the second switch is configured based on the cache coherent protocol.
4 . The system of claim 3 , wherein the second switch comprises a network switch configured based on the cache coherent protocol.
5 . The system of claim 1 , wherein the second switch is configured to discover the first computing device.
6 . The system of claim 1 , wherein the second switch is configured to cause the first computing device to reboot.
7 . The system of claim 1 , wherein the second switch is configured to cause the first switch to disable the first memory device.
8 . The system of claim 1 , wherein the second switch is configured to transmit the first data request from a second computing to the first computing device, and to perform flow control on data associated with the first data request.
9 . The system of claim 1 , further comprising a second computing device and a third computing device connected to the second switch, wherein:
the second switch is configured to:
receive a first packet associated with the first data request, from the second computing device;
receive a second packet, from the third computing device;
group the first packet and the second packet to generate a grouped packet; and
transmit the grouped packet to the first computing device.
10 . The system of claim 1 , wherein the first memory device comprises volatile memory and the second memory device comprises persistent memory.
11 . The system of claim 10 , wherein the first switch is configured to virtualize the first memory device and the second memory device.
12 . The system of claim 11 , wherein the first memory device comprises flash memory, and the first switch is configured to provide a flash translation layer for the flash memory.
13 . The system of claim 1 , wherein the first switch is included in a circuit board connected to an interface of the first computing device, the circuit board further comprising a memory module interface, the first memory device being connected to the first switch via the memory module interface.
14 . The system of claim 13 , wherein the memory module interface is associated with a solid state drive.
15 . The system of claim 13 , wherein:
the first switch is connected to the second switch through a connector, and
the connector is on the circuit board.
16 . In a system comprising a first computing device having a first switch including a processing device configured to adhere to a cache coherent protocol, and a first memory device and a second memory device connected to the first switch, wherein the first memory device is associated with a first memory technology and the second memory device is associated with a second memory technology different from the first memory technology, the system further comprising a second switch connected to the first computing device, a method comprising:
receiving a first data request and a second data request by the second switch, wherein the first data request and the second data request adhere to the cache coherent protocol;
providing the first data request and the second data request to the processing device of the first switch;
based on receiving the first data request:
identifying, by the processing device, the first memory device based on the first data request;
translating, by the processing device, the first data request into a third data request based on the first memory technology, wherein the third data request adheres to a first memory protocol different from the cache coherent protocol;
transmitting, by the processing device, the third data request to the first memory device for accessing the first memory device;
based on receiving the second data request:
identifying, by the processing device, the second memory device based on the second data request;
translating, by the processing device, the second data request to a fourth data request based on the second memory technology, wherein the fourth data request adheres to a second memory protocol different from the first memory protocol and the cache coherent protocol; and
transmitting, by the processing device, the fourth data request to the second memory device for accessing the second memory device.
17 . The method of claim 16 , wherein the first data request includes a remote direct memory access (RDMA) request, the method further comprising:
receiving, by the first switch, the RDMA request; and
sending, by the first switch, a RDMA response.
18 . The method of claim 17 , wherein the second switch receives the RDMA request from a second computing device, and transmits the RDMA request to the first switch.
19 . The method of claim 16 , wherein the translating of the first data request includes translating a virtual memory address to a physical memory address, the method further comprising:
retrieving, by the first switch, data from the first memory device at the physical memory address.
20 . The method of claim 16 further comprising:
receiving, by the second switch, a first packet associated with the first data request from second computing device;
receiving, by the second switch, a second packet from a third computing device;
grouping the first packet and the second packet to generate a grouped packet; and
transmitting, by the second switch, the grouped packet to the first computing device.