Coherent node controller

1. A cache coherent node controller comprising:

a network interface controller (NIC) that includes an integrated network interface configured for communication using a first port in an integrated circuit,

a coherent interface (CIF) configured for communication with a microprocessor, wherein the coherent interface uses a second port in the integrated circuit that is different from the first port,

a plurality of interconnected protocol engines (PE), and

a plurality of coherent link layers connected to the plurality of interconnected protocol engines, wherein a first coherent link layer of the plurality of coherent link layers provides the coherent interface, and

wherein the network interface controller is connected with the plurality of coherent link layers.

2. A computer system comprising:

a node connected to a plurality of network switches,

wherein the node comprises:

a cache coherent node controller comprising an integrated circuit, wherein the integrated circuit comprises:

a network interface controller that includes an integrated network interface,

wherein the integrated network interface is configured for communication over at least one network switch among the plurality of network switches using a first port in the integrated circuit,

a coherent interface configured for communication with a microprocessor,

wherein the coherent interface uses a second port in the integrated circuit for communication with the microprocessor and that is different from the first port, and

a plurality of interconnected protocol engines (PE).

3. The computer system according to claim 2 , wherein the integrated circuit in the cache coherent node controller further comprises:

a plurality of coherent link layers connected to the plurality of interconnected protocol engines, wherein a first coherent link layer of the plurality of coherent link layers provides the coherent interface.

4. The computer system according to claim 3 , wherein the network interface controller is connected with the plurality of coherent link layers.

5. The computer system according to claim 3 , wherein the integrated network interface of the cache coherent node controller is connected to one network switch to form a 1-dimensional fat tree topology.

6. The computer system according to claim 3 , wherein the integrated circuit in the cache coherent node controller further comprises a plurality of integrated network interfaces, wherein the plurality of integrated network interfaces are connected to two network switches to form a 2-dimensional fat tree topology.

7. The computer system according to claim 3 , wherein the integrated circuit in the cache coherent node controller further comprises a plurality of integrated network interfaces, wherein the plurality of integrated network interfaces are connected to three network switches to form a 3-dimensional fat tree topology.

8. The computer system according to claim 3 , wherein the integrated circuit in the cache coherent node controller further comprises a plurality of integrated network interfaces, wherein the plurality of integrated network interfaces are connected to four network switches to form a 4-dimensional fat tree topology.

9. The computer system according to claim 3 , wherein the integrated circuit in the cache coherent node controller further comprises n network interfaces connected to n network switches to form an n-dimensional fat tree topology.

10. The computer system according to claim 2 , wherein the plurality of network switches are selected from a group consisting of: an Omnipath switch, an InfiniBand switch, a Gen-Z switch or an Ethernet switch.

11. The computer system according to claim 2 , wherein connection between the node and the plurality of network switches is provided by fiber optic links to the plurality of network switches.

12. A cache coherent node controller comprising:

a first network interface controller comprises a first integrated network interface;

a second network interface controller comprising a second integrated network interface,

wherein the first integrated network interface and the second integrated network interface are configured for communication with a plurality of nodes in a high performance computing (HPC) system using a first plurality of ports in an integrated circuit;

a first coherent interface configured for communication with a first microprocessor over a first coherent link layer; and

a second coherent interface configured for communication with a second microprocessor over a second coherent link layer,

wherein the first coherent interface and the second coherent interface are configured for communication with the first microprocessor and the second microprocessor using a second plurality of ports in the integrated circuit that are different from the first plurality of ports.