Enabling sync header suppression latency optimization in the presence of retimers for serial interconnect
Methods and apparatuses associated with a secure stream protocol for a serial interconnect are disclosed herein. In embodiments, an apparatus comprises a transmitter and a receiver. The transmitter and receiver are configured to transmit and receive transaction layer data packets through a link, the transaction layer data packets including indicators associated with transmission of order set transmitted after a predetermined number of data blocks, when the transmission is during a header suppression mode. Additional features and other embodiments are also disclosed.
1. An apparatus comprising:
a multi-protocol multiplexer to receive at least one of first information of a first interconnect protocol or second information of a second interconnect protocol, the multi-protocol multiplexer to direct the at least one of the first information or the second information to a physical layer; and
the physical layer coupled to the multi-protocol multiplexer, wherein the physical layer is to receive the first information of the first interconnect protocol and transmit a packet on a plurality of lanes of a serial interconnect, the packet comprising a protocol ID and payload information comprising a plurality of flits,
wherein the physical layer is to:
send the protocol ID in 8-bit chunks on two consecutive lanes of the plurality of lanes, wherein the protocol ID is to be sent prior to each of the plurality of flits;
send the plurality of flits on the plurality of lanes; and
send an ordered set after a predetermined number of data blocks, during a mode in which sync headers are suppressed.
2. The apparatus of claim 1 , wherein the plurality of lanes comprises 16 lanes.
3. The apparatus of claim 1 , wherein the physical layer is to send the ordered set after 340 data blocks.
4. The apparatus of claim 1 , wherein the physical layer is to send the ordered set comprising a SKP ordered set.
5. The apparatus of claim 1 , wherein the physical layer is to send the ordered set comprising a control SKP ordered set.
6. The apparatus of claim 1 , wherein the physical layer is to send the plurality of flits having a 528-bit flit width.
7. The apparatus of claim 1 , wherein the first interconnect protocol comprises a Peripheral Component Interconnect Express protocol and the second interconnect protocol comprises a memory protocol.
8. The apparatus of claim 1 , wherein the physical layer is to send an electrical idle ordered set when a data stream is to be exited.
9. A method comprising:
receiving, in a common physical layer (PHY) of an integrated circuit, from a multi-protocol multiplexer coupled to the common PHY, information of at least one of a first interconnect protocol or a second interconnect protocol;
sending the information in a packet, from the common PHY, to a destination component via a link, the packet comprising a protocol ID and payload information comprising a plurality of flits, wherein sending the information comprises:
sending the protocol ID in 8-bit chunks on two consecutive lanes of the plurality of lanes, prior to each of the plurality of flits;
sending the plurality of flits on the plurality of lanes; and
sending an ordered set after a predetermined number of data blocks, during a mode in which sync headers are suppressed.
10. The method of claim 9 , further comprising sending the ordered set after 340 data blocks.
11. The method of claim 9 , further comprising sending the ordered set comprising a SKP ordered set.
12. The method of claim 9 , further comprising sending the ordered set comprising a control SKP ordered set.
13. The method of claim 9 , further comprising sending the plurality of flits having a 528-bit flit width.
14. The method of claim 9 , further comprising sending an electrical idle ordered set when a data stream is to be exited.
15. A system comprising:
a central processing unit (CPU) having:
at least one core; and
a physical layer to receive first information of a first interconnect protocol and output a packet on a plurality of lanes of a link, the packet comprising a protocol ID and payload information comprising a plurality of flits,
wherein the physical layer is to:
send the protocol ID in 8-bit chunks on two consecutive lanes of the plurality of lanes, prior to each of the plurality of flits;
send the plurality of flits on the plurality of lanes; and
send an ordered set after a predetermined number of data blocks, during a mode in which sync headers are suppressed;
a retimer coupled to the CPU via the link; and
an accelerator coupled to the retimer.
16. The system of claim 15 , wherein the plurality of lanes comprises 16 lanes.
17. The system of claim 15 , wherein the physical layer is to send the ordered set after 340 data blocks.
18. The system of claim 15 , wherein the physical layer is to send the ordered set comprising a SKP ordered set.
19. The system of claim 15 , wherein the physical layer is to send the ordered set comprising a control SKP ordered set.
20. The system of claim 15 , wherein the physical layer is to send the plurality of flits having a 528-bit flit width.