IP Library › Granted Patent US 12,418,429
Granted Patent B2
US 12,418,429 · App. 16/202,079 · Granted Sep 16, 2025

Modular system (switch boards and mid-plane) for supporting 50G or 100G ethernet speeds of FPGA+SSD

Inventor: Sompong Paul Olarig (Pleasanton, CA)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H04L12/04G06F30/331H03K19/1733H04L12/44G06F13/385G06F13/4022H04L2012/445
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Quick Facts
Patent No.
US 12,418,429
App. No.
16/202,079
Filed
Nov 27, 2018
Granted
Sep 16, 2025
Kind
B2
Art Unit
2184
USPC
710/313
Abstract

A chassis front-end is disclosed. The chassis front-end may include a switchboard including an Ethernet switch, a Baseboard Management Controller, and a mid-plane connector. The chassis front-end may also include a mid-plane including at least one storage device connector and a speed logic to inform at least one storage device of an Ethernet speed of the chassis front-end. The Ethernet speeds may vary.

Claims (45)

1. An Ethernet device, comprising:

a switch element, a processor, and a mid-plane connector to connect to a mid-plane; and

the mid-plane including at least one storage device connector to connect to at least one storage device and a speed logic to inform the at least one storage device of a speed of the Ethernet device, the Ethernet device supporting a first Ethernet speed and a second Ethernet speed,

wherein the Ethernet device communicates over an Ethernet connection with a second device at the speed of the Ethernet device; and

wherein the storage device configures itself based at least in part on the speed of the Ethernet device received from the speed logic.

2. The Ethernet device according to claim 1 , wherein the at least one storage device includes at least one Solid State Drive (SSD).

3. The Ethernet device according to claim 2 , wherein the speed logic includes a Complex Programmable Logic Device (CPLD) that communicates with the at least one SSD using the at least one storage device connector.

4. The Ethernet device according to claim 3 , wherein the CPLD uses at least one speed pin on the at least-one storage device connector to inform the at least one SSD of the speed of the Ethernet connection.

5. The Ethernet device according to claim 3 , wherein the CPLD uses at least one General Purpose Input/Output (GPIO) pin on the at least-one storage device connector to inform the at least one SSD of the speed of the Ethernet connection, the at least one GPIO pin latched after informing the at least one SSD of the speed of the Ethernet connection.

6. The Ethernet device according to claim 2 , wherein:

the speed logic is configured to write the speed of the Ethernet connection into a Vital Product Data (VPD) of an Electrically Erasable Programmable Read-Only Memory (EEPROM); and

the at least one SSD is configured to read the speed of the Ethernet connection from the VPD of the EEPROM.

7. The Ethernet device according to claim 2 , wherein the mid-plane further includes a wireless transmitter to transmit the speed of the Ethernet connection to the at least one SSD.

8. The Ethernet device according to claim 2 , wherein the speed logic is configured to write the speed of the Ethernet connection to a register in a Field Programmable Gate Array (FPGA) of the at least one SSD via the at least one storage device connector.

9. The Ethernet device according to claim 2 , further comprising a second switch element, a second processor, and a second mid-plane connector to connect to the mid-plane,

wherein the at least one SSD is a dual port SSD and communicates with the switch element and the second switch element via the at least one storage device connector and the mid-plane.

10. A method, comprising:

determining a speed of an Ethernet connection of an Ethernet switch at a speed logic from an Ethernet device, the Ethernet device supporting a first Ethernet speed and a second Ethernet speed; and

informing, by the speed logic, a storage device in the Ethernet device of the speed of the Ethernet connection,

wherein the Ethernet device communicates over the Ethernet connection with a second device at the speed of the Ethernet device, and

wherein the storage device configures itself based at least in part on the speed of the Ethernet device received from the speed logic.

11. The method according to claim 10 , wherein informing, by the speed logic, the storage device in the Ethernet device of the speed of the Ethernet connection includes informing, by the speed logic, a Solid State Drive (SSD) in the Ethernet device of the speed of the Ethernet connection.

12. The method according to claim 11 , wherein informing, by the speed logic, a Solid State Drive (SSD) in the Ethernet device of the speed of the Ethernet connection includes:

informing a Complex Programmable Logic Device (CPLD) by the speed logic of the speed of the Ethernet connection; and

informing, by the CPLD, the SSD in the Ethernet device of the speed of the Ethernet connection.

13. The method according to claim 12 , wherein informing, by the CPLD, the SSD in the Ethernet device of the speed of the Ethernet connection includes using at least one speed pin on a storage device connector connecting the SSD to the Ethernet device.

14. The method according to claim 12 , wherein informing, by the CPLD, the SSD in the Ethernet device of the speed of the Ethernet connection includes:

using at least one General Purpose Input/Output (GPIO) pin on a storage device connector connecting the SSD to the Ethernet device; and

latching the at least one GPIO pin latched after informing the SSD of the speed of the Ethernet connection.

15. The method according to claim 11 , wherein informing, by the speed logic, a storage device in the Ethernet device of the speed of the Ethernet connection includes writing, by the speed logic, the Ethernet speed of the Ethernet switch to a Vital Product Data (VPD) of an Electrically Erasable Programmable Read-Only Memory (EEPROM),

wherein the SSD is configured to read the speed of the Ethernet connection from the VPD of the EEPROM.

16. The method according to claim 11 , wherein informing, by the speed logic, a storage device in the Ethernet device of the speed of the Ethernet connection includes wirelessly transmitting the speed of the Ethernet connection from the speed logic to the SSD.

17. The method according to claim 11 , wherein informing, by the speed logic, a storage device in the Ethernet device of the speed of the Ethernet connection includes writing, by the speed logic, the speed of the Ethernet connection to a register in a Field Programmable Gate Array (FPGA) of the SSD using a storage device connector.

18. The method according to claim 11 , wherein:

the Ethernet device includes a first switchboard, a second switchboard, and a mid-plane, the mid-plane including a storage device connector, the mid-plane connected to the first switchboard and the second switchboard; and

the SSD is a dual port SSD and communicates with both the first switchboard and the second switchboard via the storage device connector and the mid-plane.

19. A storage device, comprising:

data storage to store data;

a controller to manage reading and writing data to the data storage;

a storage device connector to connect the storage device to a mid-plane in a chassis, the storage device connector including one or more pins;

a bit file storage to store at least two Ethernet speed bit files; and

a mapping logic to map the data from the data storage to the one or more pins on the storage device connector responsive to one of the at least two Ethernet speed bit files.

20. The storage device according to claim 19 , wherein the storage device is a Solid State Drive (SSD).

21. The Ethernet device according to claim 1 , wherein the storage device configures itself based at least in part on the speed of the Ethernet device received from the speed logic using an Ethernet speed bit file stored on the storage device.

22. The method according to claim 10 , wherein the storage device configures itself based at least in part on the speed of the Ethernet device received from the speed logic using an Ethernet speed bit file stored on the storage device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2019
From: OLARIG, SOMPONG PAUL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 048486/0672 →
Continuity (5)
Continuation In Part 15256495 · Sep 2, 2016
Provisional Application 62366622 · Jul 26, 2016
Provisional Application 62638040 · Mar 2, 2018
Provisional Application 62745967 · Oct 15, 2018
Related Publication 20190109720A1 · Apr 11, 2019
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