Fabric-backplane enterprise servers with pluggable I/O sub-system
A Cost-Reduced Enterprise Server (CRES) system includes a flexible resource-efficient server having a plurality of Processor Memory Boards (PMBs) coupled to an Input/Output Module (IOM). The IOM provides all networking and storage interfaces for the server. The IOM is implemented as a field-replaceable pluggable module, and thus all Input/Output (I/O) capabilities or resources of a CRES system may be upgraded via replacement of the IOM. Each PMB is dividable into a pair of Symmetric MultiProcessor (SMP) complexes, and each complex is coupled to a respective portion of the I/O resources provided by the IOM. Each portion of the IOM provides a pair of I/O daughter-module connectors compatible with standard I/O interfaces, such as Peripheral Component Interconnect (PCI)-X and PCI-Express. One or more CRES systems may be coupled to one or more Enterprise Server (ES) systems to form a multi-chassis server managed collectively as one or more provisioned servers.
1. A server comprising:
a physical serial bus;
a plurality of Processor Memory Boards (PMBs), each PMB comprising a plurality of physically paritionable symmetric multiprocessors, wherein each of the plurality of PMBs is dividable into a pair of symmetric multiprocessor complexes; and
an Input/Output Module (IOM) comprising a pluggable module implementing a plurality of Input/Output Sub-Modules (IOSMs), each IOSM providing an Input/Output chain of a plurality of different interfaces including a Southbridge interface, wherein each Southbridge interface of each IOSM is coupled with a virtual access controller, wherein the virtual access controller provides a physical serial interface to the physical serial bus, wherein each pair of symmetric multiprocessor complexes is coupled to a different one of the IOSMs, and wherein each of the physically partitionable symmetric multiprocessors is enabled to boot from a device accessible through the IOM.
2. The server of claim 1 , wherein the device is a DVD drive.
3. The server of claim 1 , wherein each of the physically partitionable symmetric multiprocessors is enabled to access the device.
4. The server of claim 3 , wherein the access is to update control processor firmware.
5. The server of claim 1 , wherein each of the physically partitionable symmetric multiprocessors is coupled to the physical serial bus via a respective Southbridge chip.
6. The server of claim 1 , wherein the IOM provides all networking and storage interfaces for the server.
7. The server of claim 1 , wherein each of the pair of symmetric multiprocessor complexes is coupled with a respective portion of resources provided through the networking and storage interfaces of the IOM.
8. The server of claim 7 , wherein dividing of each PMB and associating each pair of PMBs to the respective portions of resources is directed through a Graphical User Interface (GUI).
9. The server of claim 8 , wherein the dividing of each PMB and the associating each pair of PMBs to the respective portions of resources through the GUI is further directed from a client of the server.