Automatic clock configuration system
A method for automatic clock configurations is performed by a system having a host and a peripheral device. The host indicates on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports a first clock configuration. The peripheral device receives from the first GPIO whether the host supports the first clock configuration. The peripheral device selects, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device. The peripheral device selects, in response to the host not supporting the first clock configuration, use of a common clock of the host.
1. A method for automatic clock configurations, by a peripheral device, comprising:
receiving, from a host on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports the first clock configuration;
selecting, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device;
selecting, in response to the host not supporting the first clock configuration, use of a common clock of the host;
receiving, from the host on a second GPIO of the peripheral interface, whether the host supports a second clock configuration; and
formatting a reference clock signal with a bypass mode if the host supports the second clock configuration, or with a phase-locked loop (PLL) mode if the host does not support SSC mode, based upon an indication of the second GPIO.
2. The method of claim 1 , wherein the first GPIO is configured by a Basic Input/Output System (BIOS) of the host.
3. The method of claim 1 , wherein the first clock configuration is Separate Reference Clock Independent Spread (SRIS).
4. The method of claim 1 , further comprising selecting, in response to the host supporting Common Clock SSC, clock buffer bypass mode.
5. The method of claim 1 , further comprising selecting, in response to the host not supporting Common Clock SSC, clock buffer phase-locked loop (PLL) mode.
6. The method of claim 1 , wherein the peripheral interface is one of a Serial Attached Small Computer System Interface (SAS), mini SAS, or mini SAS HD.
7. A system for automatic clock configurations, comprising:
a host;
a peripheral device; and
a peripheral interface connecting the host and the peripheral device having a first general-purpose input/output (GPIO) and a second GPIO,
wherein the host is configured to indicate on the first GPIO whether the host supports a first clock configuration, wherein the first clock configuration is Separate Reference Clock Independent Spread (SRIS), and
wherein the peripheral device is configured to:
select, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device; and
select, in response to the host not supporting the first clock configuration, use of a common clock of the host;
wherein the host is further configured to indicate on the second GPIO of the peripheral interface, whether the host supports a second clock configuration.
8. The system of claim 7 , wherein the first GPIO is configured by a Basic Input/Output System (BIOS) of the host.
9. The system of claim 7 , wherein the second clock configuration is Common Clock Spread-Spectrum Clocking (SSC).
10. The system of claim 9 , wherein the peripheral device is further configured to select, in response to the host supporting Common Clock SSC, clock buffer bypass mode.
11. The system of claim 9 , wherein the peripheral device is further configured to select, in response to the host not supporting Common Clock SSC, clock buffer phase-locked loop (PLL) mode.
12. The system of claim 8 , wherein the peripheral interface is one of a Serial Attached Small Computer System Interface (SAS), mini SAS, or mini SAS HD.
13. A method for automatic clock configurations, by a peripheral device, comprising:
receiving, from a host on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports the first clock configuration, wherein the first clock configuration is Separate Reference Clock Independent Spread (SRIS);
selecting, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device; and
selecting, in response to the host not supporting the first clock configuration, use of a common clock of the host;
wherein the host is further configured to indicate on the second GPIO of the peripheral interface, whether the host supports a second clock configuration.
14. The method of claim 13 , wherein the first GPIO is configured by a Basic Input/Output System (BIOS) of the host.
15. The method of claim 13 , wherein the second clock configuration is Common Clock Spread-Spectrum Clocking (SSC).
16. The method of claim 15 , further comprising selecting, in response to the host supporting Common Clock SSC, clock buffer bypass mode.
17. The method of claim 15 , further comprising selecting, in response to the host not supporting Common Clock SSC, clock buffer phase-locked loop (PLL) mode.
18. The method of claim 13 , wherein the peripheral interface is one of a Serial Attached Small Computer System Interface (SAS), miniSAS, or mini SAS HD.