Granted Patent B2

US 9,640,588 · App. 14/867,185 · Granted May 2, 2017

Abstract

Claims (24)

1. A method for forming a memory cell, the method comprising:

forming a stack, wherein forming the stack includes:

forming a word line;

forming a third electrode in physical contact with the word line;

forming a switch element in physical contact with the third electrode;

forming a second electrode in physical contact with the switch element;

forming a memory element in series with the switch element, wherein the memory element is in physical contact with the second electrode, and wherein the memory element includes a memory chalcogenide; and

forming a first electrode in physical contact with the memory element;

directionally etching the first electrode;

directionally etching the memory element after directionally etching the first electrode;

directionally etching the second electrode after directionally etching the memory element;

directionally etching the switch element after directionally etching the second electrode;

selectively isotropic dry etching the switch element to change a smallest lateral dimension of the switch element after directionally etching the switch element such that the smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element;

directionally etching the third electrode after selectively isotropic dry etching the switch element; and

directionally etching the word line after directionally etching the third electrode.

2. The method of claim 1 , wherein changing the smallest lateral dimension of the switch element includes reducing the smallest lateral dimension of the switch element to be less than the smallest lateral dimension of the memory element.

3. The method of claim 1 , further comprising reducing the smallest lateral dimension of the memory element to be less than a smallest lateral dimension of at least one of the first electrode, the second electrode, and the third electrode aligned in the stack with the switch element and the memory element.

4. The method of claim 1 , further comprising reducing the smallest lateral dimension of the memory element to be less than the smallest lateral dimension of the switch element.

5. The method of claim 1 , wherein changing the smallest lateral dimension of the switch element includes reducing a cross-sectional area of the switch element in a plane perpendicular to a direction between the switch element and the memory element such that the cross-sectional area of the switch element is less than the cross-sectional area of the memory element.

6. The method of claim 5 , further comprising reducing a cross-sectional area of the switch element and the memory element in a plane perpendicular to a direction between the switch element and the memory element.

7. The method of claim 1 , further comprising reducing a cross-sectional area of the memory element in a plane perpendicular to a direction between the switch element and the memory element such that the cross-sectional area of the memory element is less than the cross-sectional area of the switch element.

8. The method of claim 1 , wherein selectively isotropic dry etching the switch element includes etching the switch element to a smallest lateral dimension that is less than a smallest lateral dimension to which the memory element is to be etched.

9. The method of claim 1 , further comprising etching, by a selective etching process, the memory element.

10. The method of claim 9 , wherein the etching, by the selective etching process, of the memory element includes etching the memory element to a smallest lateral dimension that is less than a smallest lateral dimension of the switch element.

Assignments (8)