IP Library Granted Patent US 9,792,097
Granted Patent B2
US 9,792,097 · App. 14/868,047 · Granted Oct 17, 2017

Method and apparatus for compiling regular expressions

Inventors: Paul Glendenning (Woodside, CA); Junjuan Xu (Campbell, CA)
Assignee: Micron Technology, Inc.
G06F8/41G06F8/427G06F8/443G06F8/447G06F9/444G06F17/5045G06F17/5054
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Quick Facts
Patent No.
US 9,792,097
App. No.
14/868,047
Granted
Oct 17, 2017
Kind
B2
Abstract

Apparatus, systems, and methods for a compiler are described. One such compiler converts source code into an automaton comprising states and transitions between the states, wherein the states in the automaton include a special purpose state that corresponds to a special purpose hardware element. The compiler converts the automaton into a netlist, and places and routes the netlist to provide machine code for configuring a target device.

Claims (42)

1. A machine-readable medium that is not a transitory propagating signal, the machine-readable medium including instructions that, when executed by a machine, cause the machine to perform operations comprising:

optimizing an automaton created from source code elements including combining redundant states;

mapping states of the automaton to hardware elements of a target device;

identifying at least one of a conflict or further optimization between the automaton and the hardware elements of the target device during the mapping;

modifying the automaton to resolve the at least one of the conflict or the optimization to create a modified automaton, the modified automaton including at least one of a state unrolled into multiple states or multiple states collapsed to a special purpose state corresponding to special purpose hardware element to resolve the optimization or conflict; and

mapping the modified automaton to the target device.

2. The machine-readable medium of claim 1 , wherein the target device is a parallel machine, and wherein the hardware elements are machine elements.

3. The machine-readable medium of claim 1 , wherein mapping the modified automaton to the target device includes:

converting the automaton into a netlist, wherein the netlist includes a plurality of instances, each instance corresponding to a hardware element of a target hardware device;

placing each of the instances including assigning each instance in the netlist to a hardware element of the target device; and

routing the connections between the hardware elements as a function of the netlist.

4. The machine-readable medium of claim 3 , comprising producing machine code for the target device from the routed and placed netlist.

5. The machine-readable medium of claim 1 , wherein identifying the optimization includes identifying the special purpose hardware element of the target device that performs the multiple states of the automaton, and wherein modifying the automaton to resolve the optimization includes collapsing the multiple states into the single special purpose state corresponding to the special purpose hardware element.

6. The machine-readable medium of claim 1 , wherein identifying the conflict includes identifying an in-degree limitation to a hardware element from the connections between hardware elements that is smaller than the in-degree of a state mapped to the hardware element, and wherein modifying the automaton to resolve the conflict includes dividing the state until the in-degree of each divided state is less than or equal to in-degree limitation.

7. A machine-implemented method comprising:

optimizing an automaton created from source code elements including combining redundant states;

mapping states of the automaton to hardware elements of a target device;

identifying at least one of a conflict or a further optimization between the automaton and the hardware elements of the target device during the mapping;

modifying the automaton to resolve the at least one of the conflict or the optimization to create a modified automaton, the modified automaton including at least one of a state unrolled into multiple states or multiple states collapsed to a special purpose state corresponding to special purpose hardware element to resolve the optimization or conflict; and

mapping the modified automaton to the target device.

8. The method of claim 7 , wherein identifying the optimization includes identifying the special purpose hardware element of the target device that performs the multiple states of the automaton, and wherein modifying the automaton to resolve the optimization includes collapsing the multiple states into the single special purpose state corresponding to the special purpose hardware element.

9. The method of claim 7 , wherein identifying the conflict includes identifying an in-degree limitation to a hardware element from the connections between hardware elements that is smaller than the in-degree of a state mapped to the hardware element, and wherein modifying the automaton to resolve the conflict includes dividing the state until the in-degree of each divided state is less than or equal to in-degree limitation.

10. The method of claim 7 , wherein mapping the modified automaton to the target device includes:

converting the automaton into a netlist, wherein the netlist includes a plurality of instances, each instance corresponding to a hardware element of a target hardware device;

placing each of the instances including assigning each instance in the netlist to a hardware element of the target device;

routing the connections between the hardware elements as a function of the netlist; and

producing machine code for the target device from the routed and placed netlist.

11. The method of claim 10 , wherein placing each of the instances includes grouping instances to match location constraints of corresponding hardware elements on the target device.

12. A system comprising:

a memory including instructions stored thereon; and

a processor communicatively coupled to the memory when the computer is in operation, wherein the instructions, when executed by the processor, cause the processor to:

optimize an automaton created from source code elements including combining redundant states;

map states of the automaton to hardware elements of a target device;

identify at least one of a conflict or a further optimization between the automaton and the hardware elements of the target device during the mapping;

modify the automaton to resolve the at least one of the conflict or the optimization to create a modified automaton, the modified automaton including at least one of a state unrolled into multiple states or multiple states collapsed to a special purpose state corresponding to special purpose hardware element to resolve the optimization or conflict; and

map the modified automaton to the target device.

13. The system of claim 12 , wherein to map the modified automaton to the target device includes the processor to:

convert the automaton into a netlist, wherein the netlist includes a plurality of instances, each instance corresponding to a hardware element of a target hardware device;

place each of the instances including assigning each instance in the netlist a hardware element of the target device; and

route the connections between the hardware elements as a function of the netlist.

14. The system of claim 12 , wherein to identify the optimization includes identifying the special purpose hardware element of the target device that performs the multiple states of the automaton, and wherein to modify the automaton to resolve the optimization includes collapsing the multiple states into the single special purpose state corresponding to the special purpose hardware element.

15. The system of claim 12 , wherein to identify the conflict includes identifying an in-degree limitation to a hardware element from the connections between hardware elements that is smaller than the in-degree of a state mapped to the hardware element, and wherein to modify the automaton to resolve the conflict includes dividing the state until the in-degree of each divided state is less than or equal to in-degree limitation.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (4)
Continuation 14252542 · Apr 14, 2014
Continuation 13357472 · Jan 24, 2012
Provisional Application 61436013 · Jan 25, 2011
Related Publication 20160019034A1 · Jan 21, 2016