Semiconductor device and electronic device
View Patent ↗To provide a novel semiconductor device or a semiconductor device capable of operating at high speed. The semiconductor device includes a plurality of circuits each having a function of storing data and a wiring EL. The plurality of circuits each include a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The wiring EL has a function of a back-gate of the first transistor. A potential for selecting the plurality of circuits is supplied to the wiring EL. Thus, data stored in the plurality of circuits is erased.
1. A semiconductor device comprising:
a first circuit;
a second circuit;
a third circuit;
a first wiring;
a second wiring;
a third wiring;
a third transistor;
a fourth transistor;
a fifth transistor; and
a second capacitor,
wherein the first circuit is configured to store a first data,
wherein the second circuit is configured to store a second data,
wherein the third circuit is configured to store a third data,
wherein each of the first circuit, the second circuit and the third circuit comprises a first transistor, a second transistor, and a first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor,
wherein the first wiring is electrically connected to the other of the source and the drain of each of the first transistors of the first circuit and the second circuit,
wherein the second wiring is electrically connected to a gate of the first transistors of the each of first circuit and third circuit,
wherein the first transistor of each of the first circuit, the second circuit and the third circuit includes an oxide semiconductor in a channel formation region,
wherein one of a source and a drain of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a fourth wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of third transistor and a second capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the fourth wiring,
wherein the third wiring is electrically connected to a back-gate of each of the first transistors of the first circuit, the second circuit and the third circuit, and
wherein an erase signal is input to the third wiring.
2. The semiconductor device according to claim 1 ,
wherein the first wiring is electrically connected to a terminal, and
wherein the first wiring is supplied with a signal for performing a data writing on the first circuit and the second circuit from the terminal.
3. The semiconductor device according to claim 1 , wherein a data writing is performed by supplying a potential to the first wiring in a period in which a potential of the other of the source and the drain of the first transistor of each of the first circuit and the second circuit is at a high level or a low level.
4. The semiconductor device according to claim 1 , wherein the first wiring and each of gate electrodes of the first transistors overlap each other.
5. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a display portion, a microphone, a speaker, or an operation key.
6. A semiconductor device comprising:
circuits arranged in a matrix comprising first row, second row, first column and second column; and
a first wiring;
a third transistor;
a fourth transistor;
a fifth transistor; and
a second capacitor,
wherein each of the circuits is configured to store a data,
wherein each of the circuits comprises a first transistor, a second transistor, and a capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the capacitor,
wherein the first transistor of each of the circuits includes an oxide semiconductor in a channel formation region,
wherein one of a source and a drain of the third transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to a third wiring,
wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of third transistor and a second capacitor,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the second wiring,
wherein the first wiring is electrically connected to a back-gate of each of the first transistors of the circuits, and
wherein an erase signal is input to the first wiring.
7. The semiconductor device according to claim 6 ,
wherein the wiring is electrically connected to a terminal, and
wherein the wiring is supplied with a signal for erasing the data stored in the circuits from the terminal.
8. The semiconductor device according to claim 6 , wherein the data are erased by supplying a potential to the wiring in a period in which a potential of the other of the source and the drain of the first transistor of each of the circuits is at a high level or a low level.
9. The semiconductor device according to claim 6 , wherein the first wiring and each of gate electrodes of the first transistors overlap each other.
10. An electronic device comprising:
the semiconductor device according to claim 6 ; and
a display portion, a microphone, a speaker, or an operation key.
11. The semiconductor device according to claim 1 , wherein the first circuit, the second circuit and the third circuit are memory cells of an auxiliary memory device.
12. The semiconductor device according to claim 6 , wherein the circuits are memory cells of an auxiliary memory device.
13. The semiconductor device according to claim 1 , wherein the first circuit, the second circuit and the third circuit are pixel circuits of a display device.
14. The semiconductor device according to claim 6 , wherein the circuits are pixel circuits of a display device.
15. The semiconductor device according to claim 1 , further comprising:
a sixth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of third transistor, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the fifth wiring.
16. The semiconductor device according to claim 6 , further comprising:
a sixth transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of third transistor, and
wherein the other of the source and the drain of the sixth transistor is electrically connected to the third wiring.