Plating interconnect for silicon chip
A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.
1. A silicon chip package comprising:
a front assembly having lead fingers, the lead fingers having a first end that is closest to the front assembly and a second end that is furthest from the front assembly;
a die attached on the front assembly;
a plastic pre-mold formed over the die and a portion of the first end of the lead fingers;
rigid traces formed into the plastic pre-mold, every portion of the rigid traces lying at or below a top surface of the plastic pre-mold, the rigid traces providing continuous interconnections between the die and the first end of the lead fingers; and
a mold formed over the rigid traces, the plastic pre-mold, and a portion of the first end of the lead fingers, the mold not contacting any portion of the second end of the lead fingers.
2. The silicon chip package of claim 1 , wherein trenches for the rigid traces are etched into the pre-mold by laser ablation.
3. The silicon chip package of claim 1 , wherein the first end of each lead finger is formed above a lower surface of the die, and wherein the second end of each lead finger is formed below the lower surface of the die.
4. The silicon chip package of claim 1 , wherein the die comprises bond pads that connect the rigid traces to the die.
5. The silicon chip package of claim 1 further comprising a die pad wherein the die is mounted on the die pad.
6. The silicon chip package of claim 1 , wherein the silicon chip package is a quad flat package (QFP).
7. A semiconductor die package comprising:
a die pad;
a semiconductor die attached to the die pad;
a plurality of lead fingers extending away from the die pad, each lead finger having a first end formed above the die pad and having a second end formed below the die pad;
a pre-mold material formed over the semiconductor die and a portion of the first end of each lead finger;
a plurality of rigid traces formed in the pre-mold material to connect the respective first end of each lead finger to the semiconductor die, every portion of the plurality of rigid traces lying at or below a top surface of the plastic pre-mold; and
a mold formed over the rigid traces, the pre-mold material, and a portion of the first end of the lead fingers, the mold not contacting any portion of the second end of each lead finger.
8. The semiconductor die package of claim 7 , wherein the rigid traces are formed in trenches in the pre-mold material formed by laser ablation.
9. The semiconductor die package of claim 7 , wherein the semiconductor die comprises silicon.
10. The semiconductor die package of claim 7 , wherein the die comprises bond pads that connect each respective rigid trace to the die.
11. The semiconductor die package of claim 7 , wherein each rigid trace of the plurality of rigid traces is formed in a respective trench of the pre-mold material.
12. The semiconductor die package of claim 11 , wherein each respective trench is etched in the pre-mold material.
13. The semiconductor die package of claim 7 , wherein the die package is a quad flat package (QFP).