Semiconductor structure integrated with magnetic tunneling junction and manufacturing method thereof
The present disclosure provides a semiconductor structure including a substrate, a transistor region having a gate over the substrate and a doped region at least partially in the substrate, a first metal layer over the transistor region, and a magnetic tunneling junction (MTJ) between the transistor region and the first metal layer. The present disclosure provides a method for manufacturing a semiconductor structure, including forming a transistor region over a substrate, the transistor region comprising a gate and a doped region, forming a magnetic tunneling junction (MTJ) over the transistor region, electrically coupling to the transistor region, and forming a first metal layer over the MTJ, electrically coupling to the MTJ and the transistor region.
1. A semiconductor structure, comprising:
a substrate;
a transistor region, comprising a gate over the substrate, a first doped region, and a second doped region at least partially in the substrate;
a first metal interconnect composed of copper over the transistor region, the first metal interconnect comprising a first metal via, a second metal via, and a third metal via; and
a magnetic tunneling junction (MTJ) entirely underneath the first metal interconnect and between the first doped region and the first metal via;
wherein the second metal via is directly over the second doped region; and the third metal via is directly over the gate.
2. The semiconductor structure of claim 1 , further comprising an upper electrode and a lower electrode of the MTJ, the upper electrode being under the first metal interconnect.
3. The semiconductor structure of claim 2 , wherein the lower electrode is electrically coupling to the first doped region.
4. The semiconductor structure of claim 3 , wherein the first doped region is a source or a drain.
5. The semiconductor structure of claim 2 , wherein the lower electrode is electrically coupling to the gate.
6. The semiconductor structure of claim 1 , wherein the MTJ comprises a diameter of from about 10 nm to about 60 nm from a top view perspective at a bottom surface of the MTJ.
7. The semiconductor structure of claim 1 , wherein the MTJ comprises a height of from about 150 Å to about 250 Å from a cross sectional perspective.
8. The semiconductor structure of claim 1 , wherein the first metal interconnect, the gate, the doped region, and the MTJ form a conductive loop.
9. A semiconductor structure, comprising:
a substrate;
a first transistor region, comprising a gate over the substrate and a doped region at least partially in the substrate; and
a first metal interconnect composed of copper over the first transistor region, the first metal interconnect comprising a first metal via and a second metal via;
a first magnetic tunneling junction (MTJ) between the doped region and the first metal via; and
a dielectric, surrounding the first MTJ,
wherein the second metal via connects to the gate by contacting a contact plug over the gate.
10. The semiconductor structure of claim 9 , further comprising a second transistor region adjacent to the first transistor region, a second MTJ being over the second transistor region, wherein the first MTJ and the second MTJ comprise different diameters at a bottom surface of the first MTJ and at a bottom surface of the second MTJ from a top view perspective.
11. The semiconductor structure of claim 10 , wherein an area of a first lower electrode of the first MTJ is different from an area of a second lower electrode of the second MTJ from a top view perspective.
12. The semiconductor structure of claim 10 , wherein the first MTJ and the second MTJ have an identical diameter at a bottom surface of the first MTJ and the second MTJ, respectively, from a top view perspective and different heights from a cross sectional perspective.
13. The semiconductor structure of claim 9 , wherein the first MTJ comprises a free layer and a pinned layer, the pinned layer being closer to the doped region than the free layer.
14. The semiconductor structure of claim 9 , wherein the first metal interconnect comprises a via and a conductive line, the via being electrically coupling to an upper electrode of the MTJ.
15. The semiconductor structure of claim 9 , wherein the doped region is a raised source or a raised drain.
16. A semiconductor memory structure, comprising:
a first transistor region, comprising a first gate and a first doped region;
a second transistor region at the same height level as the first transistor region, comprising a second gate and a second doped region;
an interconnect layer over the first transistor region and the second transistor region;
a first magnetic tunneling junction (MTJ) directly over and electrically connected to the first gate and under the interconnect layer.
17. The semiconductor memory structure of claim 16 , wherein the first gate is positioned under a projection of the first MTJ.
18. The semiconductor memory structure of claim 16 , further comprising a second MTJ between the second transistor region and the interconnect layer.
19. The semiconductor memory structure of claim 16 , wherein a diameter at a bottom of the first MTJ is different from a diameter at a bottom of the second MTJ from a top perspective.
20. The semiconductor memory structure of claim 16 , wherein a height of the first MTJ is different from a height of the second MTJ from a cross sectional perspective.