Method and apparatus for mapping a logical address between memories of a storage drive based on write frequency rankings
A storage drive including a first and second memories and a controller. The second memory has a write cycle lifetime that is less than a write cycle lifetime of the first memory. Each of the first and second memories includes solid-state memory. The controller: determines a write frequency for a first logical address; and based on the write frequency, determines a write frequency ranking for the first logical address. The write frequency ranking is based on a weighted time-decay average of write counts or an average of elapsed times of write cycles. The controller also: determines whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and if the write frequency ranking of the first logical address is greater, maps the logical address with the lowest write frequency ranking in the first memory to the second memory.
1. A method of operating a storage drive, wherein the storage drive comprises a first memory and a second memory, wherein a write cycle lifetime of the second memory is less than a write cycle lifetime of the first memory, and wherein each of the first memory and the second memory comprises solid-state memory, the method comprising:
receiving a first logical address from a host, wherein the host is separate from the storage drive;
determining a write frequency for the first logical address, wherein the write frequency indicates how frequently data is written to the first logical address;
based on the write frequency, determining a write frequency ranking for the first logical address, wherein the write frequency ranking is based on (i) a weighted time-decay average of write counts, or (ii) an average of elapsed times between write cycles;
determining whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory; and
if the write frequency ranking of the first logical address is greater than the lowest write frequency ranking of logical addresses of the first memory, mapping the logical address with the lowest write frequency ranking in the first memory to the second memory.
2. The method of claim 1 , wherein the mapping of the logical address with the lowest write frequency ranking in the first memory to the second memory includes mapping the logical address with the lowest write frequency ranking in the first memory from a physical address of the first memory to a physical address of the second memory.
3. The method of claim 1 , further comprising:
if the write frequency ranking of the first logical address is greater than the lowest write frequency ranking of logical addresses of the first memory, mapping the first logical address to the second memory subsequent to mapping the logical address with the lowest write frequency ranking in the first memory to the second memory; and
if the write frequency ranking of the first logical address is less than the lowest write frequency ranking of logical addresses of the first memory, mapping the first logical address to the second memory.
4. The method of claim 1 , further comprising, if the write frequency ranking of the first logical address is greater than the lowest write frequency ranking of logical addresses of the first memory, moving data at the logical address of the first memory with the lowest write frequency ranking to the second memory.
5. The method of claim 1 , wherein the write frequency ranking for the first logical address is based on the weighted time-decay average of write counts.
6. The method of claim 5 , wherein the weighted time-decay average of write counts is based on a sum of a time averaged write count at a timestep and a first product, and wherein the first product is of a write event value and a rate value.
7. The method of claim 6 , wherein:
the weighted time-decay average of write counts is based on a sum of (i) a second product of a first constant and the time averaged write count at a timestep, and (ii) the first product;
the first product is of the rate value and the write event value;
the rate value is a second constant;
the write event value is equal to (i) a first value if a write event occurred at the timestep, and (ii) a second value if a write event did not occur at the timestep;
the first constant is a decay rate constant;
the second constant is an attack rate constant; and
the first constant is equal to 1 minus the second constant.
8. The method of claim 1 , wherein the write frequency ranking for the first logical address is based on the average of the elapsed times between the write cycles.
9. The method of claim 1 , wherein the write frequency ranking for the first logical address is based on a normalized average of the elapsed times between the write cycles.
10. The method of claim 1 , wherein the lowest write frequency ranking of the first memory is greater than a highest write frequency ranking of the logical addresses of the second memory.
11. A storage drive comprising:
a first memory;
a second memory having a write cycle lifetime that is less than a write cycle lifetime of the first memory, wherein each of the first memory and the second memory comprises solid-state memory; and
a controller configured to
receive a first logical address from a host, wherein the host is separate from the storage drive,
determine a write frequency for the first logical address, wherein the write frequency indicates how frequently data is written to the first logical address,
based on the write frequency, determine a write frequency ranking for the first logical address, wherein the write frequency ranking is based on (i) a weighted time-decay average of write counts, or (ii) an average of elapsed times between write cycles,
determine whether the write frequency ranking is greater than a lowest write frequency ranking of logical addresses of the first memory, and
if the write frequency ranking of the first logical address is greater than the lowest write frequency ranking of logical addresses of the first memory, map the logical address with the lowest write frequency ranking in the first memory to the second memory.
12. The storage drive of claim 11 , wherein the controller is configured to, when mapping the logical address with the lowest write frequency ranking in the first memory to the second memory, map the logical address with the lowest write frequency ranking in the first memory from a physical address of the first memory to a physical address of the second memory.
13. The storage drive of claim 11 , wherein the controller is configured to:
if the write frequency ranking of the first logical address is greater than the lowest write frequency ranking of logical addresses of the first memory, map the first logical address to the second memory subsequent to mapping the logical address with the lowest write frequency ranking in the first memory to the second memory; and
if the write frequency ranking of the first logical address is less than the lowest write frequency ranking of logical addresses of the first memory, map the first logical address to the second memory.
14. The storage drive of claim 11 , wherein the controller is configured to, if the write frequency ranking of the first logical address is greater than the lowest write frequency ranking of logical addresses of the first memory, move data at the logical address of the first memory with the lowest write frequency ranking to the second memory.
15. The storage drive of claim 11 , wherein the write frequency ranking for the first logical address is based on the weighted time-decay average of write counts.
16. The storage drive of claim 15 , wherein the weighted time-decay average of write counts is based on a sum of a time averaged write count at a timestep and a first product, and wherein the first product is of a write event value and a rate value.
17. The storage drive of claim 16 , wherein the rate value is between 0 and 1.
18. The storage drive of claim 16 , wherein:
the weighted time-decay average of write counts is based on a sum of (i) a second product of a first constant and the time averaged write count at a timestep, and (ii) the first product;
the first product is of the rate value and the write event value; and
the rate value is a second constant.
19. The storage drive of claim 18 , wherein the first constant is between 0 and 1.
20. The storage drive of claim 18 , wherein the write event value is equal to (i) a first value if a write event occurred at the timestep, and (ii) a second value if a write event did not occur at the timestep.
21. The storage drive of claim 18 , wherein:
the first constant is a decay rate constant;
the second constant is an attack rate constant; and
the first constant is equal to 1 minus the second constant.
22. The storage drive of claim 11 , wherein the write frequency ranking for the first logical address is based on the average of the elapsed times between the write cycles.
23. The storage drive of claim 11 , wherein the write frequency ranking for the first logical address is based on a normalized average of the elapsed times between the write cycles.
24. The storage drive of claim 11 , wherein the lowest write frequency ranking of the first memory is greater than a highest write frequency ranking of the logical addresses of the second memory.
25. The storage drive of claim 11 , wherein the controller is configured to compare the write frequency ranking for the first logical address to the lowest write frequency ranking when determining whether the write frequency ranking for the first logical address is greater than the lowest write frequency ranking.