Synchronous input/output initialization exchange sequences
Aspects include for performing an initialization sequence by a first device to execute synchronous input/output (I/O) commands across a synchronous I/O link. The initialization sequence includes posting, by the first device, a first acknowledgement in response to a register area corresponding to a second device being updated with first information according to a first synchronization sequence, the first information comprising a worldwide node name of the second device and posting, by the first device, a second acknowledgement in response the register area being updated with second information according to a second synchronization sequence, the second information comprising mailbox information. The initialization sequence also includes performing, by the first device, a third synchronization sequence to provide a worldwide node name of the first device; and performing, by the first device, a fourth synchronization sequence to provide a status area address.
1. A computer program product, the computer program product comprising a computer readable storage medium having program instructions for performing an initialization sequence by a first device to execute synchronous input/output (I/O) commands across a synchronous I/O link embodied therewith, the first device comprising a processor coupled to a memory, the program instructions executable by the processor to cause the first device to perform:
posting a first acknowledgement in response to a register area corresponding to a second device being updated with first information according to a first synchronization sequence, the first information comprising a worldwide node name of the second device;
posting a second acknowledgement in response the register area being updated with second information according to a second synchronization sequence, the second information comprising mailbox information;
performing a third synchronization sequence to provide a worldwide node name of the first device; and
performing a fourth synchronization sequence to provide a status area address,
wherein the worldwide node name of the second device, the worldwide node name of the first device, the mailbox information, the status area address are utilized to execute the synchronous I/O commands across the synchronous I/O link.
2. The computer program product of claim 1 , wherein the first device is a server.
3. The computer program product of claim 1 , wherein the second device is a storage control unit.
4. The computer program product of claim 1 , wherein the posting of the first acknowledgement initiates the second device to execute the second synchronization sequence.
5. The computer program product of claim 1 , wherein the program instructions are further executable by the processor to cause:
receiving a third acknowledgement in response to completing the third synchronization sequence.
6. The computer program product of claim 1 , wherein the program instructions are further executable by the processor to cause:
receiving a value in a synchronous operation and acknowledgement field of the register area, the value specifying that the first information is present and valid; and
posting the first acknowledgement in response to receiving the value.
7. The computer program product of claim 1 , wherein the mailbox comprises a mailbox base address register through which a mailbox is written by the first device via the synchronous I/O commands.
8. The computer program product of claim 1 , wherein the status area address specifies an address of a status area of the first device.
9. The computer program product of claim 1 , wherein the program instructions are further executable by the processor to cause:
restarting the initialization sequence upon detection of an error,
wherein the initialization sequence includes the first, second, third, and fourth synchronization sequences.
10. A system, comprising a processor and a memory storing program instructions for performing an initialization sequence to execute synchronous input/output (I/O) commands across a synchronous I/O link thereon, the program instructions executable by the processor to cause the system to perform:
posting a first acknowledgement in response to a register area corresponding to a device being updated with first information according to a first synchronization sequence, the first information comprising a worldwide node name of the device;
posting a second acknowledgement in response the register area being updated with second information according to a second synchronization sequence, the second information comprising mailbox information;
performing a third synchronization sequence to provide a worldwide node name of the system; and
performing a fourth synchronization sequence to provide a status area address,
wherein the world wide node name of the device, the world wide node name of the system, the mailbox information, the status area address are utilized to execute the synchronous I/O commands across the synchronous I/O link.
11. The system of claim 10 , wherein the system is a server.
12. The system of claim 10 , wherein the second device is a storage control unit.
13. The system of claim 10 , wherein the posting of the first acknowledgement initiates the second device to execute the second synchronization sequence.
14. The system of claim 10 , wherein the program instructions are further executable by the processor to cause the system to perform:
receiving a third acknowledgement in response to completing the third synchronization sequence.
15. The system of claim 10 , wherein the program instructions are further executable by the processor to cause the system to perform:
receiving a value in a synchronous operation and acknowledgement field of the register area, the value specifying that the first information is present and valid; and
posting the first acknowledgement in response to receiving the value.
16. The system of claim 10 , wherein the mailbox comprises a mailbox base address register through which a mailbox is written by the first device via the synchronous I/O commands.
17. The system of claim 10 , wherein the status area address specifies an address of a status area of the first device.
18. The system of claim 10 , wherein the program instructions are further executable by the processor to cause the system to perform:
restarting the initialization sequence upon detection of an error,
wherein the initialization sequence includes the first, second, third, and fourth synchronization sequences.