Field-effect transistor and fabricating method thereof
A method for fabricating a field-effect transistor is provided. The method includes: forming a gate dielectric layer and a barrier layer on a substrate in sequence; forming a first silicon layer on and in contact with the barrier layer; performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer; and forming a second silicon layer on and in contact with the first silicon layer.
1. A method for fabricating a field-effect transistor comprising:
forming a gate dielectric layer and a barrier layer on a substrate in sequence;
forming a first silicon layer on and in contact with the barrier layer;
performing a thermal treatment to form a silicide layer between the barrier layer and the first silicon layer;
forming a second silicon layer on and in contact with the first silicon layer;
patterning the second silicon layer, the first silicon layer, the barrier layer and the gate dielectric layer to form a dummy gate structure; and
forming a metal gate electrode to take the place of a patterned second silicon layer and a patterned first silicon layer.
2. The method for fabricating the field-effect transistor according to claim 1 , wherein the thermal treatment comprises a spike annealing process or a soak annealing process.
3. The method for fabricating the field-effect transistor according to claim 1 , wherein the second silicon layer has a thickness substantially greater than that of the first silicon layer.
4. The method for fabricating the field-effect transistor according to claim 3 , wherein the first silicon layer has a thickness substantially ranging from 40 Å to 200 Å.
5. The method for fabricating the field-effect transistor according to claim 1 , further comprising performing at least one ion implant process on the substrate to form a source/drain structure in the substrate prior to the forming of the metal gate electrode.
6. The method for fabricating the field-effect transistor according to claim 5 , wherein the step of forming the metal gate electrode to take the place of the patterned second silicon layer and the patterned first silicon layer comprises:
removing the patterned second silicon layer and the patterned first silicon layer to form an opening in the dummy gate structure;
forming at least one U-shaped work function layer on sidewalls of the opening; and
forming a metal layer on the U-shaped work function layer, so as to fill the opening.
7. The method for fabricating the field-effect transistor according to claim 6 , wherein a titanium-rich surface is formed on the barrier layer and in contact with the silicide layer after the thermal treatment is carried out.
8. The method for fabricating the field-effect transistor according to claim 7 , wherein the silicide layer is partially or completely removed by the step of removing the patterned second silicon layer and the patterned first silicon layer.