IP Library Granted Patent US 9,601,384
Granted Patent B2
US 9,601,384 · App. 14/874,652 · Granted Mar 21, 2017

Method of forming a semiconductor device comprising first and second nitride layers

Inventor: Kanta Saino (Tokyo, JP)
Assignee: Micron Technology, Inc.
H01L21/823462H01L21/761H01L21/76229H01L21/823481H01L27/10814H01L27/10823H01L27/10855H01L27/10876H01L29/0649H01L21/76834H01L21/76838
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Quick Facts
Patent No.
US 9,601,384
App. No.
14/874,652
Granted
Mar 21, 2017
Kind
B2
Abstract

A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Claims (57)

1. A method of forming a semiconductor device, comprising:

forming a plurality of isolation regions on a semiconductor substrate that are laterally spaced from one another by semiconductive material of the semiconductor substrate in a straight line vertical cross section;

forming a first stack over a first portion of the semiconductor substrate, the first stack comprising hafnium and metal, the first stack having a first terminating edge that is over one of the spaced isolation regions in the straight line vertical cross section;

forming a second stack over a second portion of the semiconductor substrate the second stack comprising hafnium and metal, the second stack having a second terminating edge that is over the one spaced isolation region and is spaced from the first terminating edge in the straight line vertical cross section;

forming a conductive layer over the first and second stacks and over the one isolation region between the first and second terminating edges in the straight line vertical cross section;

forming a first nitride layer over the conductive layer by using a first deposition method;

forming a second nitride layer over the first nitride layer by using a second deposition method different from the first disposition method; and

removing a portion of the second nitride layer, a portion of the first nitride layer, a portion of the conductive layer, a portion of the second stack and a portion of the first stack, so as to form a third stack, a fourth stack and a fifth stack, the third stack comprising a material of the first stack, the conductive layer, the first and second nitride layers, the fourth stack comprising a material of the second stack, the conductive layer, the first and second nitride layers, the fifth stack comprising the conductive layer and the first and second nitride layers and placed between the third and fourth stacks over the one isolation region in the straight line vertical cross section.

2. The method as claimed in claim 1 , wherein the first deposition method is an atomic layer deposition.

3. The method as claimed in claim 1 , wherein the first deposition method is a low pressure chemical vapor deposition.

4. The method as claimed in claim 3 , wherein the second deposition method is a plasma chemical vapor deposition.

5. The method as claimed in claim 1 , the method further comprising:

forming a first contact plug beside the third stack.

6. The method as claimed in claim 5 , the method further comprising:

forming a second contact plug beside the fifth stack.

7. The method as claimed in claim 6 , the method further comprising:

forming a conductive wiring over the third, fourth and fifth stacks and the first and second contact plugs, so that the conductive wiring is electively connected to the first and second contact plugs.

8. The method as claimed in claim 1 , wherein the conductive layer is formed such that the conductive layer comprises a seam in the fifth stack over the one isolation region in the straight line vertical cross section.

9. A method of forming a semiconductor device, comprising:

forming an isolation region on a semiconductor substrate;

forming a first stack over a first portion of the semiconductor substrate and on a first portion of the isolation region, the first stack comprising hafnium and metal;

forming a second stack over a second portion of the semiconductor substrate and a second portion of the isolation region, the second portion of the isolation region being apart from the first portion of the isolation region via a third portion thereof, the second stack comprising hafnium and metal;

forming a conductive layer over the first and second stacks and the third portion of the isolation region;

forming a first nitride layer over the conductive layer by using a first deposition method;

forming a second nitride layer over the first nitride layer by using a second deposition method different from the first disposition method;

removing a portion of the second nitride layer, a portion of the first nitride layer, a portion of the conductive layer, a portion of the second stack and a portion of the first stack, so as to form a third stack, a fourth stack and a fifth stack, the third stack comprising a material of the first stack, the conductive layer, the first and second nitride layers, the fourth stack comprising a material of the second stack, the conductive layer, the first and second nitride layers, the fifth stack comprising the conductive layer and the first and second nitride layers and placed between the third and fourth stacks over the third portion of the isolation region; and

the conductive layer is formed such that the conductive layer comprises a seam over the third portion of the isolation region, the first nitride layer is formed so as to fill the seam.

10. A method of forming a semiconductor device, comprising:

forming a first insulating layer comprising Hafnium over a semiconductor substrate comprising an isolation region dividing the semiconductor substrate into first and second portions;

forming a first metal layer over the first insulating layer;

removing a portion of the first insulating layer and a portion of the first metal layer to form a first stack including the first insulating layer and the first metal layer over the first portion of the semiconductor substrate, an end of the first stack being positioned over the isolation region;

forming a second insulating layer comprising Hafnium over the first stack, the second portion of the semiconductor substrate and the isolation region;

forming a second metal layer over the second insulating layer;

removing a portion of the second insulating layer and a portion of the second metal layer to form a second stack including the second insulating layer and the second metal layer over the second portion of the semiconductor substrate, an end of the second stack being positioned over the isolation region and apart from the end of the first stack;

forming a conductive layer over the first and second stacks and the isolation region;

forming a first nitride layer over the conductive layer by using a first deposition method;

forming a second nitride layer over the first nitride layer by using a second deposition method different from the first disposition method; and

removing a portion of the second nitride layer, a portion of the first nitride layer, a portion of the conductive layer, a portion of the second stack and a portion of the first stack, so as to form a third stack, a fourth stack and a fifth stack, the third stack comprising a material of the first stack, the conductive layer, the first and second nitride layers, the fourth stack comprising a material of the second stack, the conductive layer, the first and second nitride layers, the fifth stack comprising the conductive layer and the first and second nitride layers and placed between the third and fourth stacks over the isolation region.

11. The method as claimed in claim 10 , wherein the first deposition method is an atomic layer deposition.

12. The method as claimed in claim 10 , wherein the first deposition method is a low pressure chemical vapor deposition.

13. The method as claimed in claim 12 , wherein the second deposition method is a plasma chemical vapor deposition.

14. The method as claimed in claim 10 , the method further comprising:

forming a first contact plug beside the third stack.

15. The method as claimed in claim 14 , the method further comprising:

forming a second contact plug beside the fifth stack.

16. The method as claimed in claim 15 , the method further comprising:

forming a conductive wiring over the third, fourth and fifth stacks and the first and second contact plugs, so that the conductive wiring is electively connected to the first and second contact plugs.

17. The method as claimed in claim 10 , wherein the conductive layer is formed such that the conductive layer comprises a seam over the isolation region.

18. The method as claimed in claim 17 , wherein the first nitride layer is formed so as to fill the seam.

19. A method of forming a semiconductor device, comprising:

forming a conductive layer over a semiconductor substrate to cover first and second stacks each comprising hafnium and metal over the semiconductor substrate, the first and second stacks being placed apart from each other over an isolation region formed on the semiconductor substrate,

the conductive layer being also formed to cover the isolation region;

forming a first nitride layer over the conductive layer by using a first deposition method;

forming a second nitride layer over the first nitride layer by using a second deposition method different from the first disposition method;

removing a portion of the second nitride layer, a portion of the first nitride layer, a portion of the conductive layer, a portion of the second stack and a portion of the first stack, so as to form a third stack, a fourth stack and a fifth stack, the third stack comprising a material of the first stack, the conductive layer, the first and second nitride layers, the fourth stack comprising a material of the second stack, the conductive layer, the first and second nitride layers, the fifth stack comprising the conductive layer and the first and second nitride layers and placed between the third and fourth stacks over the isolation region; and

the conductive layer is formed such that the conductive layer comprises a seam over the third portion of the isolation region, the first nitride layer is formed so as to fill the seam.

20. The method as claimed in claim 19 , wherein the first deposition method is an atomic layer deposition.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Priority Claims (1)
JP 2013-171305 · Aug 21, 2013 · national
Continuity (2)
Continuation 14450674 · Aug 4, 2014
Related Publication 20160027701A1 · Jan 28, 2016