Solid state storage device with variable logical capacity based on memory lifecycle
Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, wherein the first logical memory capacity is less than the physical memory capacity, determine that at least one of the memory regions is at or near end of life, and in response to the determination, (1) retire the at least one of the memory regions and (2) reduce a logical memory capacity of the host device to a second logical memory capacity that is less than the first logical memory capacity.
1. A memory device, comprising:
a plurality of memory regions collectively defining a physical memory capacity; and
a controller operably coupled to the memory regions, wherein the controller is configured to—
advertise a first logical memory capacity to a host device, wherein the first logical memory capacity is less than the physical memory capacity,
determine that at least one of the memory regions is at or near end of life,
in response to the determination:
send a notification to the host device that a logical memory capacity of the memory device will be reduced,
after sending the notification, retire the at least one of the memory regions, and
reduce the logical memory capacity of the memory device to a second logical memory capacity that is less than the first logical memory capacity, whereby the memory device with the reduced logical capacity is recognized as a different device by the host device.
2. The memory device of claim 1 wherein the controller is further configured to advertise the second logical memory capacity to the host device in lieu of the first logical memory capacity.
3. The memory device of claim 1 wherein the controller is further configured to send a notification to the host device indicating that the at least one of the memory regions is at or near end of life, and prompting the host device to transfer contents of the at least one of the memory regions to one or more other memory regions of the plurality of memory regions.
4. The memory device of claim 1 wherein the controller is further configured to determine that the at least one of the memory regions is at or near end of life based on a write count associated with the at least one of the memory regions.
5. The memory device of claim 1 wherein the controller is further configured to determine that the at least one of the memory regions is at or near end of life based on a bit error rate associated with the at least one of the memory regions.
6. The memory device of claim 1 wherein the memory regions comprises NAND flash memory media.
7. The memory device of claim 1 wherein the controller is further configured to:
directly access the memory regions via a first set of memory addresses;
map individual ones of the first memory addresses to second memory addresses implemented by the host device for accessing the memory regions via the controller; and
permanently remove memory addresses from the set of second memory addresses to a reduced set of memory addresses after retiring the at least one of the memory regions.
8. The memory device of claim 7 wherein the controller is further configured to renumber the reduced set of memory addresses.
9. The memory device of claim 1 , wherein the first and second logical memory capacities exclude an over-provisioning (OP) space within the plurality of memory regions, wherein the OP space is used in wear leveling for spreading write degradation evenly across the plurality of memory regions.
10. The memory device of claim 9 , wherein the controller is configured to:
provision a first set of memory blocks to the OP space in association with the first logical memory capacity; and
in response to the determination, provision a second set of memory blocks to the OP space in association with the second logical memory capacity, wherein the second set includes a different combination of memory blocks than the first set.
11. The memory device of claim 9 , wherein the controller is configured to maintain availability within the OP space by reducing the logical memory capacity and by provisioning the second set of memory blocks to the OP in response to the determination.
12. The memory device of claim 1 , wherein the controller is configured to permanently reduce the logical memory capacity of the memory device to the second logical memory capacity, wherein the permanent reduction precludes the host device from (1) reversing the logical memory capacity to the first logical memory capacity and (2) accessing the at least one of the memory regions determined to be at or near end of life.
13. The memory device of claim 12 , wherein the permanent reduction prevents the controller from reverting the logical memory capacity back to the first logical memory capacity.
14. The memory device of claim 12 , wherein the controller is further configured to maintain a mapping table used to translate between physical addresses and logical addresses, wherein:
the physical addresses identify locations within the plurality of memory regions and correspond to the physical memory capacity,
the logical addresses identify memory locations for the host device, and
maintaining the mapping table includes, in response to the determination, eliminating from the mapping table (1) a portion of the physical addresses and (2) corresponding logical addresses, wherein resulting logical addresses correspond to the second logical memory capacity.
15. The memory device of claim 14 , wherein the controller is configured to eliminate the portion of the physical addresses and the corresponding logical addresses from the mapping table without an intervention from the host device, without notifying the host device, without a confirmation from the host device, without an authorization from the host device, or a combination thereof.
16. A controller for operably coupling a host device to a storage device that has a physical memory capacity, the controller comprising:
a processor; and
internal memory coupled to the processor and including instructions that, when executed by the processor, performs a method that includes:
advertising a first logical memory capacity to the host device, wherein the first logical memory capacity (1) represents a storage capacity of the storage device that is accessible to the host device and (2) is less than the physical memory capacity,
determining that at least one memory regions in the storage device is at or near end of life,
in response to the determination:
sending a notification to the host device that a logical memory capacity of the storage device will be reduced,
after sending the notification, retiring the at least one of the memory regions, and
reducing the logical memory capacity of the storage device to a second logical memory capacity that is less than the first logical memory capacity, whereby the memory device with the reduced logical capacity is recognized as a different device by the host device.
17. The controller of claim 16 , wherein the instructions correspond to the method further comprising:
provisioning a first set of memory blocks in the storage device to an over-provisioning (OP) space in association with the first logical memory capacity, wherein the OP is reserved for wear leveling within the storage device to spread write degradation evenly across memory regions therein; and
in response to the determination, provisioning a second set of memory blocks to the OP space in association with the second logical memory capacity, wherein the second set includes a different combination of memory blocks than the first set.
18. The controller of claim 16 , wherein the instructions correspond to the method further comprising:
maintaining a mapping table used to translate between physical addresses and logical addresses, wherein:
the physical addresses identify locations within the storage device and correspond to the physical memory capacity,
the logical addresses identify memory locations for the host device, and
maintaining the mapping table includes, in response to the determination, eliminating from the mapping table (1) a portion of the physical addresses and (2) corresponding logical addresses, wherein resulting logical addresses correspond to the second logical memory capacity.
19. The controller of claim 18 , wherein the portion of the physical addresses and the corresponding logical addresses are eliminated without an intervention from the host device, without notifying the host device, without a confirmation from the host device, without an authorization from the host device, or a combination thereof.