Semiconductor device and lead frame used for the same
A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.
1. A semiconductor memory device, comprising:
an element-mounting region;
a semiconductor memory element mounted on the element-mounting region via an adhesive layer;
a rectangular region sealing the semiconductor memory element with resin;
an element-supporting portion supporting the semiconductor memory element;
a plurality of first hanging elements provided at a first long edge side of the rectangular region, one end of each of the first hanging elements being connected to the element-supporting portion, and a second end of each of the first hanging elements being exposed to a first lateral face of the resin containing the first long edge of the rectangular region;
an outer lead portion including a plurality of outer leads arranged at first and second short edge sides of the rectangular region; and
an inner lead portion including a plurality of inner leads, at least a part of the inner leads being routed in the element-mounting region, and one end of at least one of the inner leads being arranged at a second long edge side of the rectangular region,
wherein at least a part of the element-supporting portion is in the element-mounting region,
wherein the inner leads includes first inner leads and second inner leads,
wherein each of the first inner leads includes at least a first portion, a second portion, and a third portion, the first portion extending to the one end of the inner leads, the second portion extending to the outer leads arranged at the first short edge side, and the third portion routing in the element-mounting region to extend in a direction which intersects the first and second portions,
wherein each of the second inner leads includes at least a fourth portion, a fifth portion, and a sixth portion, the fourth portion extending to the one end of the inner leads, the fifth portion extending to the outer leads arranged at the second short edge side, and the sixth portion routing in the element-mounting region to extend in a direction which intersects the fourth and fifth portions, and
wherein at least a part of the element-supporting portion is provided in a region between the third portion and the sixth portion.
2. The semiconductor memory device according to claim 1 , further comprising:
a second hanging element provided at the second long edge side, one end of the second hanging element being connected to the element-supporting portion, and the other end of the second hanging element being exposed to a second lateral face of the resin containing the second long edge of the rectangular region.
3. The semiconductor memory device according to claim 2 , wherein the element-supporting portion includes a first supporting element and a second supporting element.
4. The semiconductor memory device according to claim 3 , wherein the first hanging elements extend from the first supporting element to the first long edge.
5. The semiconductor memory device according to claim 3 , wherein the second hanging element extends from the second supporting element to the second long edge.
6. The semiconductor memory device according to claim 1 , wherein the element-supporting portion includes an opening.
7. The semiconductor memory device according to claim 6 , wherein the opening has a elongate shape, and a longer direction of the opening corresponds to a direction of the long edge of the rectangular region.
8. The semiconductor memory device according to claim 1 , wherein the semiconductor memory element includes electrode pads for connecting to the inner leads using wires.
9. The semiconductor memory device according to claim 8 , wherein the wires are connected to surfaces of the inner leads on which the semiconductor memory element is mounted.
10. The semiconductor memory device according to claim 8 , wherein at least one of the inner leads extends beyond the element-mounting region toward the second long edge side.
11. The semiconductor memory device according to claim 1 , wherein at least a part of the element-supporting portion is connected to at least one of the inner leads electrically.