Power semiconductor package having vertically stacked driver IC
View Patent ↗In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier.
1. A semiconductor package comprising:
a control carrier having a die side and an opposite input/output (I/O) side;
a control FET attached to said die side of said control carrier;
a driver integrated circuit (IC) for driving said control FET, said driver IC situated over said control FET and electrically coupled to said control FET by at least one conductive buildup layer.
2. The semiconductor package of claim 1 , further comprising:
a sync carrier having another die side and another opposite input/output (I/O) side;
a sync FET attached to said another die side of said sync carrier.
3. The semiconductor package of claim 1 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said control carrier by bondwire.
4. The semiconductor package of claim 1 , wherein said driver IC is flip chip mounted over said at least one conductive buildup layer.
5. The semiconductor package of claim 1 , wherein said control FET comprises a silicon FET.
6. The semiconductor package of claim 1 , wherein said control FET comprises a III-Nitride FET.
7. A semiconductor package comprising:
a sync carrier having a die side and an opposite input/output (I/O) side;
a sync FET attached to said die side of said sync carrier;
a driver integrated circuit (IC) for driving said sync PET, said driver IC situated over said sync FET and electrically coupled to said sync FET by at least one conductive buildup layer.
8. The semiconductor package of claim 7 , further comprising:
a control carrier having another die side and another opposite input/output (I/O);
a control FET attached to said another die side of said control carrier.
9. The semiconductor package of claim 7 , wherein said driver IC is electrically coupled to said at least one conductive buildup layer formed over said sync carrier by bondwire.
10. The semiconductor package of claim 7 , wherein said driver IC is flip chip mounted over said at least one conductive buildup layer.
11. The semiconductor package of claim 7 , wherein said sync FET comprises a silicon FET.
12. The semiconductor package of claim 7 , wherein said sync FET comprises a III-Nitride FET.