Double sided NMOS/PMOS structure and methods of forming the same
A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the dielectric layer, and a first Metal Oxide-Semiconductor (MOS) transistor of a first conductivity type. The first MOS transistor includes a first gate dielectric overlying and contacting the first semiconductor layer, and a first gate electrode overlying the first gate dielectric. A second semiconductor layer is underlying and bonded to the bottom surface of the dielectric layer. A second MOS transistor of a second conductivity type opposite to the first conductivity type includes a second gate dielectric underlying and contacting the second semiconductor layer, and a second gate electrode underlying the second gate dielectric.
1. A method comprising:
forming a first transistor at a top surface of a Semiconductor-On-Insulator (SOI) substrate, wherein the SOI substrate comprises:
a dielectric layer;
a first semiconductor layer;
a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are bonded to opposite surfaces of the dielectric layer, and the first transistor is formed on the second semiconductor layer;
thinning the first semiconductor layer;
forming a second transistor on the first semiconductor layer, wherein the first transistor and the second transistor are of opposite conductivity types; and
forming a through-via penetrating through the first semiconductor layer, the dielectric layer, and the second semiconductor layer.
2. The method of claim 1 , wherein the thinning the first semiconductor layer comprises:
implanting hydrogen ions into the first semiconductor layer to form a hydrogen-concentrated layer in the first semiconductor layer; and
cleaving the first semiconductor layer along the hydrogen-concentrated layer to separate the first semiconductor layer into two layers.
3. The method of claim 1 , wherein the first semiconductor layer and the second semiconductor layer have different surface orientations.
4. The method of claim 3 , wherein the second semiconductor layer has a (100) surface orientation, and the first transistor is an n-type transistor, and wherein the first semiconductor layer has a (110) surface orientation, and the second transistor is a p-type transistor.
5. The method of claim 4 further comprising forming additional transistors on the first semiconductor layer and the second semiconductor layer, wherein all transistors formed on the top surface of the first semiconductor layer are p-type transistors, and all transistors formed on a top surface of the second semiconductor layer are n-type transistors.
6. The method of claim 1 , wherein at a time after the through-via is formed, no transistor that is of a conductivity type opposite to a conductivity type of the first transistor is formed on the second semiconductor layer, and wherein no transistor that is of a conductivity type opposite to a conductivity type of the second transistor is formed on the first semiconductor layer.
7. The method of claim 1 further comprising forming a first interconnect structure and a second interconnect structure on opposite sides of the SOI substrate, wherein the first interconnect structure and the second interconnect structure are electrically inter-coupled by the through-via.
8. The method of claim 1 , wherein the SOI substrate and the through-via are comprised in a first chip, and wherein the method further comprises bonding a second chip to the first chip.
9. The method of claim 1 further comprising forming a first isolation region penetrating through the first semiconductor layer, wherein the through-via further penetrates through the first isolation region.
10. The method of claim 9 further comprising forming a second isolation region penetrating through the second semiconductor layer, wherein the through-via further penetrates through the second isolation region.
11. A method comprising:
thinning a first semiconductor layer in a Semiconductor-On-Insulator (SOI) substrate, wherein the SOI substrate comprises:
the first semiconductor layer;
a dielectric layer having a first surface bonded to the first semiconductor layer, wherein the dielectric layer is a continuous layer with no distinguishable interface therein; and
a second semiconductor layer bonded to a second surface of the dielectric layer;
forming a first transistor and a second transistor on the first semiconductor layer and the second semiconductor layer, respectively; and
forming a through-via penetrating through the first semiconductor layer, the dielectric layer, and the second semiconductor layer, wherein the through-via electrically couples the first transistor to the second transistor.
12. The method of claim 11 further comprising forming a first isolation region penetrating through the first semiconductor layer, with the first isolation region contacting the dielectric layer, wherein the through-via further penetrates through the first isolation region.
13. The method of claim 12 further comprising forming a second isolation region penetrating through the second semiconductor layer, with the second isolation region contacting the dielectric layer, wherein the through-via further penetrates through the second isolation region.
14. The method of claim 11 further comprising:
forming a first inter-layer dielectric, with a first gate of the first transistor located in the first inter-layer dielectric; and
forming a second inter-layer dielectric, with a second gate of the second transistor located in the second inter-layer dielectric, wherein the through-via penetrates through both the first inter-layer dielectric and the second inter-layer dielectric.
15. The method of claim 11 , wherein the thinning the first semiconductor layer comprises:
implanting hydrogen ions into the first semiconductor layer to form a hydrogen-concentrated layer in the first semiconductor layer; and
cleaving the first semiconductor layer along the hydrogen-concentrated layer to separate the first semiconductor layer into two layers, wherein the first transistor is formed at a surface of the first semiconductor layer, with the surface of the first semiconductor layer generated by the cleaving.
16. The method of claim 11 further comprising:
forming a first transistor on the first semiconductor layer; and
forming a second transistor on the second semiconductor layer, wherein the first transistor and the second transistor are of opposite conductivity types, and the first semiconductor layer and the second semiconductor layer have different surface orientations.
17. A method comprising:
forming first isolation regions in a first semiconductor layer of a Semiconductor-On-Insulator (SOI) substrate, wherein the SOI substrate comprises:
a dielectric layer;
a first semiconductor layer;
a second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are bonded to opposite surfaces of the dielectric layer, wherein the first isolation regions penetrate through the first semiconductor layer to contact the dielectric layer;
forming second isolation regions penetrating through the second semiconductor layer to contact the dielectric layer;
forming a through-via penetrating through the dielectric layer, a first one of the first isolation regions, and a second one of the second isolation regions;
forming a first transistor on the first semiconductor layer; and
forming a second transistor on the second semiconductor layer, wherein the first transistor and the second transistor are of opposite conductivity types, and the first semiconductor layer and the second semiconductor layer have different surface orientations.
18. The method of claim 17 , wherein the first semiconductor layer has a first surface and a second surface opposite to the first surface, wherein the second surface contacts the dielectric layer, and the first surface is substantially level with a surface of the first isolation regions.
19. The method of claim 18 , wherein the second semiconductor layer has a third surface and a fourth surface opposite to the third surface, wherein the fourth surface contacts the dielectric layer, and the third surface is substantially level with a surface of the second isolation regions.
20. The method of claim 17 further comprising, when both the first semiconductor layer and the second semiconductor layer are bonded to the dielectric layer, thinning the first semiconductor layer.