IP Library › Granted Patent US 9,299,637
Granted Patent B2
US 9,299,637 · App. 14/878,596 · Granted Mar 29, 2016

Semiconductor module

Inventor: Takafumi Yamada (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/3735H01L23/3675H01L23/49811H01L23/49838H01L24/32H01L2224/29111H01L2224/32225H01L2924/014H01L2924/01047H01L2924/01051
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Quick Facts
Patent No.
US 9,299,637
App. No.
14/878,596
Granted
Mar 29, 2016
Kind
B2
Abstract

The semiconductor module includes a pin that is connected to a semiconductor element; a pin wiring substrate that has a second metal film and a first metal film on the upper and lower surfaces, the first metal film and the second metal film being electrically bonded to the pin; solder that bonds the pin and the semiconductor element; a DCB substrate that has a third metal film and a fourth metal film on the upper and lower surfaces, the third metal film being bonded to a lower surface of the semiconductor element; and a first cooler that is connected to the fourth metal film. The ratio H/T of a height H of the solder to a distance T from the semiconductor element to the first metal film is equal to or greater than 0.2 and equal to or less than 0.7.

Claims (14)

1. A semiconductor module comprising:

a semiconductor element;

a pin electrically and thermally connected to an upper surface of the semiconductor element;

a pin wiring substrate including a pin wiring insulating substrate, a first metal film provided on a lower surface of the pin wiring insulating substrate, and a second metal film provided on an upper surface of the pin wiring insulating substrate, the first metal film and the second metal film being electrically bonded to the pin;

solder bonding the pin and the semiconductor element;

a DCB substrate including a ceramic insulating substrate, a third metal film bonded to a lower surface of the semiconductor element and provided on an upper surface of the ceramic insulating substrate, and a fourth metal film provided on a lower surface of the ceramic insulating substrate; and

a first cooler thermally connected to the fourth metal film,

wherein a ratio H/T of a height H of the solder to a distance T from the semiconductor element to the first metal film of the pin wiring insulating substrate is equal to or greater than 0.2 and equal to or less than 0.7.

2. The semiconductor module according to claim 1 , wherein the pin includes a plurality of pin members connected to the semiconductor element through the solder, and

the height H of the solder is the height from an interface between the semiconductor element and the solder to a lowest surface of an upper portion of the solder between the plurality of pins.

3. The semiconductor module according to claim 1 , wherein a linear expansion coefficient of the solder is less than 22.0 ppm/K.

4. The semiconductor module according to claim 1 , wherein the solder is SnSb-based solder.

5. The semiconductor module according to claim 4 , wherein the SnSb-based solder includes 13 mass % of Sb as a main component.

6. The semiconductor module according to claim 1 , wherein the solder is SnAg-based solder.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2015
From: YAMADA, TAKAFUMI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 036759/0893 →
Priority Claims (1)
JP 2013-225513 · Oct 30, 2013 · national
Continuity (2)
Continuation PCTJP2014074484 · Sep 17, 2014
Related Publication 20160027716A1 · Jan 28, 2016