Semiconductor arrangement
View Patent ↗A semiconductor arrangement comprising a substrate having a first trench formed therein, a field plate layer arranged to extend within the first trench and coat the first trench, the field plate layer having a thickness such that it defines a second trench within the first trench, a barrier layer arranged to coat an internal surface of the second trench; and a trench fill material configured to substantially planarize the first and second trenches.
1. A semiconductor arrangement comprising:
a substrate having a first trench formed therein;
a field plate layer arranged to extend along a base and a plurality of side walls within the first trench, the field plate layer having a thickness on the side walls so that the field plate layer defines a second trench within the side walls of the first trench; and
a trench fill material configured to substantially planarize the first and second trenches wherein the arrangement includes a barrier layer arranged to coat an internal surface of the second trench between the field plate layer and the trench fill material,
wherein the semiconductor arrangement includes a further barrier layer in the first trench between the substrate and the field plate layer, wherein the further barrier layer comprises the same material as the barrier layer.
2. The semiconductor arrangement of claim 1 , wherein the field plate layer is of the same material as the trench fill material.
3. The semiconductor arrangement of claim 1 , wherein the barrier layer is electrically insulating relative to the field plate layer.
4. The semiconductor arrangement of claim 1 , wherein the barrier layer comprises an oxide.
5. The semiconductor arrangement of claim 1 , wherein the barrier layer comprises a nitride.
6. The semiconductor arrangement of claim 1 , wherein the field plate layer comprises polycrystalline silicon and/or the trench fill material comprises polycrystalline silicon.
7. The semiconductor arrangement of claim 1 , wherein the field plate layer is doped to at least 1×10 17 cm −3 .
8. A semiconductor component including a semiconductor arrangement comprising:
a substrate having a first trench formed therein;
a field plate layer arranged to extend along a base and a plurality of side walls within the first trench, the field plate layer having a thickness on the side walls so that the field plate layer defines a second trench within the first trench, wherein the second trench extends in parallel along the base and the side walls of the first trench, and includes an area within the field plate layer between the side walls; and
a trench fill material arranged to fill the area within the field plate layer between the side walls and substantially planarize the first and second trenches, wherein the arrangement includes a barrier layer to coat an internal surface of the second trench between the field plate layer and the trench fill material,
wherein the semiconductor arrangement includes a further barrier layer in the first trench between the substrate and the field plate layer, wherein the further barrier layer comprises the same material as the barrier layer.
9. An electronic device comprising a semiconductor component, the semiconductor component comprising:
a substrate having a first trench formed therein;
a field plate layer arranged to extend along a base and a plurality of side walls within the first trench, the field plate layer having a thickness on the side walls so that the field plate layer defines a second trench within the side walls of the first trench; and
a trench fill material arranged to substantially planarize the first and second trenches, wherein the arrangement includes a barrier layer to coat an internal surface of the second trench between the field plate layer and the trench fill material,
wherein the semiconductor component includes a further barrier layer in the first trench between the substrate and the field plate layer, wherein the further barrier layer comprises the same material as the barrier layer.