Stressed channel bulk fin field effect transistor
Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
1. A method of forming a semiconductor structure comprising:
forming a plurality of semiconductor fins directly on a first portion of a top surface of a single crystalline material layer;
forming a dielectric material layer having a top surface below a horizontal plane including said top surfaces of said plurality of semiconductor fins;
forming a gate structure straddling said plurality of semiconductor fins directly on said dielectric material layer, said gate structure including a vertical stack of a gate dielectric and a gate electrode;
forming at least one dielectric material portion by patterning said dielectric material layer employing said gate structure as an etch mask, wherein said at least one dielectric material portion is located directly on a second portion of said top surface of said single crystalline material layer and laterally between each semiconductor fin of said plurality of semiconductor fins; and
forming a gate spacer directly on sidewalls of said gate structure and sidewalls of said at least one dielectric material portion and a third portion of said top surface of said single crystalline material layer.
2. The method of claim 1 , wherein each sidewall of said at least one dielectric material portion is in physical contact with a sidewall of said plurality of semiconductor fins.
3. The method of claim 1 , further comprising removing physically exposed portions of said plurality of semiconductor fins by an etch process that employs a combination of said gate structure and said gate spacer as an etch mask.
4. The method of claim 3 , wherein physically exposed sidewalls of said plurality of semiconductor fins after said etch process are vertically coincident with outer sidewalls of said gate spacer.
5. The method of claim 1 , further comprising forming a source region and a drain region over said single crystalline material layer by depositing at least one semiconductor material by a selective epitaxy process, wherein said source region is formed directly on first sidewalls of said plurality of semiconductor fins, and said drain region is formed directly on second sidewalls of said plurality of semiconductor fins.
6. The method of claim 5 , wherein said at least one semiconductor material is deposited directly on exposed portions of said top surface of said single crystalline material layer.
7. The method of claim 5 , wherein each of said source region and said drain region is single crystalline, and is epitaxially aligned to a single crystalline material within said single crystalline material layer.
8. The method of claim 7 , wherein said source region and said drain region comprise a doped semiconductor material having a lattice constant that is different from a lattice constant of said single crystalline material, and apply a stress to portions of said plurality of semiconductor fins that are present after formation of said source region and said drain region.
9. The method of claim 5 , further comprising:
forming a source-side intrinsic semiconductor material portion directly on a fourth portion of said top surface of said single crystalline material layer; and
forming a drain-side intrinsic semiconductor material portion directly on a fifth portion of said top surface of said single crystalline material layer, wherein said source region is formed directly on said source-side intrinsic semiconductor material portion and said drain region is formed directly on said drain-side intrinsic semiconductor material portion.
10. The method of claim 1 , wherein each sidewall of said at least one dielectric material portion is vertically coincident with a sidewall of said gate structure upon patterning of said dielectric material layer.
11. The method of claim 1 , wherein said at least one dielectric material portion has a bottommost surface that is coplanar with a bottommost surface of each semiconductor fin of said plurality of semiconductor fins.
12. The method of claim 1 , wherein said single crystalline material layer is a rare-earth oxide material.
13. The method of claim 12 , wherein said rare-earth oxide comprises a rare earth element selected from La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu.