Memory device architecture
Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.
1. A method, comprising:
forming a plurality of row drivers and a plurality of column drivers below and within a footprint of an array of memory cells.
2. The method of claim 1 , wherein forming the plurality of row drivers and the plurality of column drivers comprises partitioning the plurality of row drivers into a plurality of subsets of row drivers and partitioning the plurality of column drivers into a plurality of subsets of column drivers and interspersing the plurality of subsets of row drivers among the plurality of subsets of column drivers.
3. The method of claim 2 , wherein forming the plurality of row drivers and the plurality of column drivers comprises forming word line drivers and bit line drivers.
4. The method of claim 2 , wherein forming the plurality of row drivers and the plurality of column drivers comprises distributing the plurality of row drivers and the plurality of column drivers across the footprint of the array in disjointed row driver regions and disjointed column driver regions, such that row electrodes connecting the plurality of row drivers to memory cells of the array are staggered, and column electrodes connecting the plurality of column drivers to the memory cells of the array are staggered.
5. The method of claim 4 , wherein distributing the plurality of row drivers and the plurality of column drivers comprises grouping row drivers into the row driver regions and grouping column drivers into the column driver regions such that the row electrodes and the column electrodes are staggered in bundles.
6. The method of claim 4 , further comprising connecting each row electrode to a central part of one of the row driver regions and connecting each column electrode to a central part of one of the column driver regions.
7. The method of claim 4 , wherein distributing row drivers and column drivers comprises forming a repeating quilt-like pattern of the row driver regions and column driver regions.
8. The method of claim 7 , wherein forming the repeating quilt-like pattern comprises forming the row driver regions such that they border on the column driver regions.
9. The method of claim 1 , further comprising:
forming one or more interconnect levels over a circuit level, the circuit level comprising the plurality of row drivers and the plurality of column drivers; and
forming the array of memory cells over the one or more interconnect levels.
10. The method of claim 9 , wherein the forming the array of memory cells over the one or more interconnect levels comprises forming an array of phase change memory cells between row electrodes and column electrodes in a cross-point memory array.
11. The method of claim 9 , wherein forming the array of memory cells over the one or more interconnect levels comprises scaling the array to cover logic circuitry in the circuit level for the array.