Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-κ dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.
1. A semiconductor device, comprising:
a substrate having at least one semiconductor fin;
an insulating structure disposed above the substrate and separated from the semiconductor fin to form a gap therebetween;
a gate stack covering at least a portion of the semiconductor fin and at least disposed in the gap between the insulating structure and the semiconductor fin, wherein the gate stack comprises:
a high-κ dielectric layer covering the semiconductor fin and spaced apart from the insulating structure;
a gate electrode disposed above the high-κ dielectric layer and at least in the gap between the insulating structure and the semiconductor fin; and
a metal layer disposed between the high-κ dielectric layer and gate electrode, wherein a portion of the metal layer is sandwiched between the high-κ dielectric layer and the insulating structure; and
a gate spacer disposed adjacent the gate stack and in contact with the metal layer.
2. The semiconductor device of claim 1 , wherein the metal layer of the gate stack covers a sidewall of the insulating structure.
3. The semiconductor device of claim 1 , wherein the gap is adjacent to the gate spacer.
4. The semiconductor device of claim 1 , further comprising a gate insulating film present between the semiconductor fin and the gate stack.
5. The semiconductor device of claim 1 , wherein the insulating structure has a sidewall facing the semiconductor fin, and the sidewall of the insulating structure is uncovered by the gate spacer.
6. The semiconductor device of claim 1 , wherein the gate spacer is further in contact with the high-κ dielectric laer.
7. The semiconductor device of claim 1 , wherein the gate spacer is further in contact with the insulating structure.
8. A semiconductor device, comprising:
a substrate having at least one semiconductor fin;
an isolation structure disposed on the substrate and adjacent to the semiconductor fin;
an insulating structure disposed above the isolation structure and laterally separated from the semiconductor fin to form a gap therebetween, the gap having at least one inner surface; and
a gate stack covering at least a portion of the semiconductor fin and at least disposed in the gap between the insulating structure and the semiconductor fin, wherein the gate stack comprises:
a high-κ dielectric layer covering the semiconductor fin and leaving at least a portion of the inner surface of the gap uncovered;
a gate electrode disposed above the high-κ dielectric layer and at least in the gap between the insulating structure and the semiconductor fin; and
a metal layer between the high-κ dielectric layer and the gate electrode and in contact with the isolation structure.
9. The semiconductor device of claim 8 , wherein the metal layer of the gate stack covers the inner surface of the gap.
10. The semiconductor device of claim 8 , further comprising at least two gate spacers respectively disposed on opposite sides of the gate stack and opposite sides of the insulating structure.
11. The semiconductor device of claim 10 , wherein the gap is present between the at least two gate spacers.
12. The semiconductor device of claim 8 , further comprising a gate insulating film present between the semiconductor fin and the gate stack.
13. The semiconductor device of claim 8 , wherein the insulating structure is further in contact with the high-κ dielectric layer.
14. The semiconductor device of claim 8 , wherein the insulating structure is further in contact with insulating structure.
15. A semiconductor device, comprising:
a substrate having at least one semiconductor fin;
an insulating structure disposed on the substrate and spaced apart from the semiconductor fin, the insulating structure having a sidewall facing the semiconductor fin;
a high-κ dielectric layer disposed on the semiconductor fin and separated from the insulating structure;
a metal layer disposed on the high-κ dielectric layer and in contact with the sidewall of the insulating structure and the high-κ dielectric layer; and
a gate electrode disposed on the metal layer.
16. The semiconductor device of claim 15 , wherein the sidewall of the insulating structure is uncovered by the high-κ dielectric layer.
17. The semiconductor device of claim 15 , wherein a portion of the metal layer is disposed between the insulating structure and the high-κ dielectric layer.
18. The semiconductor device of claim 15 , further comprising a gate insulating film disposed between the high-κ dielectric layer and the semiconductor fin.
19. The semiconductor device of claim 18 , wherein the gate insulating film is in contact with the semiconductor fin and the high-κ dielectric layer.
20. The semiconductor device of claim 15 , further comprising a gate spacer adjacent to the gate electrode and in contact with the metal layer.