Logical address history management in memory device
Some embodiments include apparatuses and methods including memory cells and a control unit to store information in a portion of the memory cells and to generate an entry associated with the information. The information is associated with a logical address recognized by a host. The entry includes an indicator indicating that the information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host.
1. An apparatus comprising:
memory cells; and
a control unit coupled to an interface, the interface including a connector to couple to a host through a connection, the interface including circuitry to receive first information and second information, the control unit to store the first information in a first portion of the memory cells and to generate a first entry associated with the first information, the information associated with a logical address recognized by the host, the host including a host controller, the entry including an indicator indicating that the first information is to be preserved for a creation of an image of information associated with logical addresses in a logical address space recognized by the host;
the control unit to store the second information in a second portion of the memory cells after the first information is stored in the first portion of the memory cells, and to generate a second entry associated with the second information, wherein the second information is associated the same logical address as the first information, and the image of the first information is request by the host after the second information is stored; and
the control unit is configured to invalidate the first information if the host controller of the host sends a command to indicate that the first information is to be invalidated, wherein control unit is configured to perform an operation to consolidate the first information and the second information, and the first information stored in the first portion of the memory cells and the second information stored in the second portion of the memory cells remain valid after the operation until the host controller indicates that the first information stored in the first portion of the memory cells and the second information stored in the second portion of the memory cells are invalid.
2. The apparatus of claim 1 , wherein the additional entry includes an additional indicator indicating that the second information is to be preserved for a creation of an additional image of information associated with the logical addresses in the logical address space recognized by the host.
3. The apparatus of claim 2 , wherein the first information stored in the first portion of the memory cells and the second information stored in the second portion of the memory cells are different information.
4. The apparatus of claim 1 , wherein the control unit does not invalidate the first information stored in the first portion of the memory cells if the host does not indicate that the first information is to be invalidated.
5. The apparatus of claim 1 , wherein the entry associated with the first information stored in the first portion of the memory cells includes at least one indicator to indicate a time and a date when the first information is stored.
6. The apparatus of claim 1 , wherein the entry associated with the first information stored in the first portion of the memory cells includes an additional indicator to indicate a version number of the information.
7. The apparatus of claim 1 , wherein the logical address includes a logical block address.
8. A method comprising:
receiving, performed by a memory device, first information associated with a logical block address;
generating, performed by the memory device, a first indicator to indicate that the first information is preserved for a creation of a first image of information that includes the first information, the first information associated with a logical address recognized by a host, the host including a host controller;
storing, performed by the memory device, the first information in a first portion of memory cells;
receiving, performed by the memory device, second information associated with the logical block address associated with the first information;
generating, performed by the memory device, a second indicator to indicate that the second information is preserved for a creation of a second image of information including the second information;
storing, performed by the memory device, the second information in a second portion of the memory cells after the first information is stored, wherein the second information is associated the same logical address as the first information, and the first image of information excludes the second information;
invalidating, performed by the memory device, the first information in response to a controller host if the host sending sends a command to indicate that the first information is to be invalidated; and
performing a consolidation operation to consolidate information stored in the memory cells without invalidating the first and second information, wherein the first information stored in the first portion of the memory cells and the second information stored in the second portion of the memory cells remain valid after the consolidation operation until the host indicates that the first information stored in the first portion of the memory cells and the second information stored in the second portion of the memory cells are invalid.
9. The method of claim 8 , wherein the second image of information includes the first information and the second information.
10. The method of claim 8 , further comprising:
receiving a command from a host to create the first image of the information.
11. The method of claim 10 , further comprising:
receiving a command from the host to create the second image of the information.