IP Library Granted Patent US 9,620,615
Granted Patent B2
US 9,620,615 · App. 14/902,516 · Granted Apr 11, 2017

IGBT manufacturing method

Inventors: Xiaoshe Deng (Wuxi New District, CN); Qiang Rui (Wuxi New District, CN); Shuo Zhang (Wuxi New District, CN); Genyi Wang (Wuxi New District, CN)
Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.
H01L29/66333H01L21/26513H01L21/31111H01L29/0611H01L29/7395
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Quick Facts
Patent No.
US 9,620,615
App. No.
14/902,516
Granted
Apr 11, 2017
Kind
B2
Abstract

An insulated gate bipolar transistor (IGBT) manufacturing method comprises the following steps: providing a semiconductor substrate of a first conducting type, the semiconductor substrate having a first major surface and a second major surface ( 100 ); forming a field-stop layer of a second conducting type on the first major surface of the semiconductor substrate ( 200 ); growing an oxide layer on the field-stop layer ( 300 ); removing the oxide layer from the field-stop layer ( 400 ); forming an epitaxial layer on the field-stop layer from which the oxide layer has been removed; and then manufacturing an IGBT on the epitaxial layer ( 600 ). Before regular manufacturing of an IGBT, the surface defects of a substrate material are eliminated as many as possible before epitaxy is formed, and the quality of an epitaxial layer is improved, thereby improving the quality of the whole IGBT.

Claims (14)

1. A method of manufacturing an IGBT (Insulated Gate Bipolar Transistor), comprising the following steps:

providing a semiconductor substrate with a first conductivity type, the semiconductor substrate having a first major surface and a second major surface;

forming a field stop layer with a second conductivity type on the first major surface of the semiconductor substrate;

growing an oxide layer on the field stop layer;

removing the oxide layer on the field stop layer;

forming an epitaxial layer on the field stop layer after the oxide layer is removed; and

manufacturing the IGBT continuously on the epitaxial layer.

2. The method according to claim 1 , wherein the semiconductor substrate with the first conductivity type is a P-type substrate material.

3. The method according to claim 1 , wherein the oxide layer has a thickness ranging from 100 to 25000 angstrom.

4. The method according to claim 1 , wherein the semiconductor substrate having the field stop layer is oxidized in a dry-oxygen of 800° C. to 1100° C., a hydrogen oxygen oxidation or a vapor oxidation environment to obtain the oxide layer.

5. The method according to claim 1 , wherein when the oxide layer is grown on the field stop layer, an oxide layer is formed simultaneously on the second major surface of the semiconductor substrate, and the method further comprises removing the oxide layer formed on the second major layer of the semiconductor substrate.

6. The method according to claim 1 , wherein a wet etching technology or a combination of a wet etching and a dry etching technology is performed to remove the oxide layer on the field layer.

7. The method according to claim 1 , wherein the field stop layer is formed on the semiconductor substrate by surface implanting N-type impurities and a high temperature drive-in technology.

8. The method according to claim 7 , wherein an implantation dose of the N-type impurities is 5E11/cm 2 to 1E15/cm 2 , and energy thereof is 30 KeV to 200 KeV.

Assignments (2)
MERGER Recorded Apr 29, 2019
From: CSMC TECHNOLOGIES FAB1 CO., LTD.
To: CSMC TECHNOLOGIES FAB2 CO., LTD.
Reel/Frame 049020/0800 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2015
From: DENG, XIAOSHE; RUI, QIANG; ZHANG, SHUO; WANG, GENYI
To: CSMC TECHNOLOGIES FAB1 CO., LTD.
Reel/Frame 037391/0895 →
Priority Claims (1)
CN 2013 1 0323481 · Jul 29, 2013 · national
Continuity (1)
Related Publication 20160380071A1 · Dec 29, 2016