IP Library Granted Patent US 10,037,896
Granted Patent B2
US 10,037,896 · App. 14/907,253 · Granted Jul 31, 2018

Electro-assisted transfer and fabrication of wire arrays

Inventors: Jeffrey Weisse (Palo Alto, CA); Xiaolin Zheng (Palo Alto, CA)
Assignee: The Board of Trustees of the Leland Stanford Junior University
H01L21/326B81C1/00031H01L21/02203H01L21/02532H01L21/02603H01L29/0676B81B2207/056
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Quick Facts
Patent No.
US 10,037,896
App. No.
14/907,253
Granted
Jul 31, 2018
Kind
B2
Abstract

A fabrication method includes: (1) forming a wire array on a fabrication substrate; (2) forming a porous layer within a portion of the fabrication substrate below the wire array; (3) separating the porous layer and the wire array from a remaining portion of the fabrication substrate; and (4) affixing top ends of the wire array to a target substrate.

Claims (15)

1. A fabrication method, comprising:

providing a substrate including a first side and an opposite, second side;

forming a patterned catalyst layer over the second side of the substrate;

providing (a) a first electrode adjacent to the first side of the substrate and (b) a second electrode adjacent to the patterned catalyst layer; and

applying a current between the first electrode and the second electrode and through the substrate in the presence of an etchant to form a wire array, wherein the current supplies charge carriers as oxidizing species that move toward the patterned catalyst layer, such that a material of the substrate adjacent to the patterned catalyst layer is oxidized and removed in the presence of the etchant.

2. The fabrication method of claim 1 , wherein the substrate is a Si wafer, and the wire array is an array of Si nanowires.

3. The fabrication method of claim 1 , wherein the substrate is a Si wafer, and the wire array is an array of Si microwires.

4. The fabrication method of claim 1 , wherein the etchant is devoid of a chemical oxidant.

5. The fabrication method of claim 1 , wherein applying the current includes modulating the current over time between a high current density and a low current density while forming the wire array.

6. The fabrication method of claim 5 , wherein the wire array has an axially modulated porosity.

7. The fabrication method of claim 5 , wherein the wire array has an axially modulated orientation.

8. The fabrication method of claim 1 , wherein forming the patterned catalyst layer over the second side of the substrate includes:

depositing discrete, masking structures over the second side of the substrate;

depositing a catalyst layer over and in between the discrete, masking structures; and

removing the discrete, masking structures to form the patterned catalyst layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: WEISSE, JEFFREY; ZHENG, XIAOLIN
To: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY
Reel/Frame 042138/0756 →
CONFIRMATORY LICENSE Recorded Oct 24, 2016
From: STANFORD UNIVERSITY
To: NAVY, SECRETARY OF THE UNITED STATES OF AMERICA
Reel/Frame 040520/0074 →
Continuity (3)
Provisional Application 61858512 · Jul 25, 2013
Provisional Application 61864364 · Aug 9, 2013
Related Publication 20160181121A1 · Jun 23, 2016