Integration of III-V devices on Si wafers
An insulating layer is conformally deposited on a plurality of mesa structures in a trench on a substrate. The insulating layer fills a space outside the mesa structures. A nucleation layer is deposited on the mesa structures. A III-V material layer is deposited on the nucleation layer. The III-V material layer is laterally grown over the insulating layer.
1. A method to manufacture an electronic device, comprising:
conformally depositing a first insulating layer around a plurality of mesa structures in a trench on a substrate;
depositing a nucleation layer on the mesa structures; and
depositing a III-V material layer on the nucleation layer, wherein the III-V material layer is laterally grown over the first insulating layer.
2. The method of claim 1 , further comprising
depositing a device layer on the laterally grown III-V material layer.
3. The method of claim 1 , wherein the III-V material layer includes gallium nitride, and the substrate includes silicon.
4. The method of claim 1 , wherein the first insulating layer includes silicon oxide, silicon nitride, or a combination thereof.
5. The method of claim 1 , wherein the nucleation layer includes AlN.
6. The method of claim 1 , further comprising
depositing a second insulating layer on the substrate;
patterning the second insulating layer;
etching the substrate through the patterned second insulating layer to form the trench.
7. The method of claim 1 , further comprising
depositing a hard mask layer within the trench;
patterning the hard mask layer; and
etching the substrate through the patterned hard mask layer to form the mesa structures; and
removing the pattered hard mask layer.
8. The method of claim 1 , wherein the first insulating layer covers a sidewall of the trench.
9. The method of claim 1 , wherein the laterally grown III-V material layer is formed in direct contact with the first insulating layer.
10. The method of claim 1 , wherein the laterally grown III-V material layer is separated from the first insulating layer by a space.
11. The method of claim 1 , further comprising:
removing portions of the III-V material layer that are directly above the nucleation layer, thereby leaving behind portions of the III-V material layer that are directly above the first insulating layer.
12. An electronic device, comprising
a plurality of mesa structures within a trench on a substrate;
an insulating layer filling a space around the mesa structures;
a nucleation layer on the mesa structures; and
a III-V material layer on the nucleation layer, wherein the III-V material layer extends laterally over the insulating layer.
13. The electronic device of claim 12 , further comprising
a device layer on the laterally extended III-V material layer.
14. The electronic device of claim 12 , wherein the III-V material layer includes GaN and the mesa structures include silicon.
15. The electronic device of claim 12 , wherein the insulating layer includes silicon oxide, silicon nitride, or a combination thereof.
16. The electronic device of claim 12 , wherein the nucleation layer includes AlN.
17. The electronic device of claim 12 , wherein the insulating layer covers a sidewall of the trench.
18. The electronic device of claim 12 , wherein at least one of the mesa structures is aligned along {0001} crystal orientation.
19. The electronic device of claim 12 , wherein the laterally extended III-V material layer is formed in direct contact with the insulating layer.
20. The electronic device of claim 12 , wherein a bottom surface of the laterally extended III-V material layer is formed not in direct contact with the insulating layer.
21. A method to manufacture an electronic device comprising:
forming a plurality of mesa structures within a trench on a substrate;
conformally depositing a first insulating layer within the trench;
depositing a nucleation layer on the mesa structures;
depositing a III-V material layer on the nucleation layer; and
laterally growing the III-V material layer from the nucleation layer over the first insulating layer.
22. The method of claim 21 , further comprising
depositing a device layer on the laterally grown III-V material layer.
23. The method of claim 21 , wherein forming the plurality of mesa structures comprises
depositing a mask layer in the trench;
patterning the mask layer; and
etching the substrate through the patterned mask layer.
24. The method of claim 21 , wherein the laterally grown III-V material layer is in a direct contact with the first insulating layer.
25. The method of claim 21 , wherein the III-V material layer is separated from the first insulating layer by a space.