FPGA power management system
An FPGA power management system includes a host power management integrated circuit connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device via a power configuration/monitoring bus. The host power management integrated circuit includes a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device. The host power management integrated circuit further includes at least one voltage regulator for supplying an output voltage to an FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block. The host power management integrated circuit further includes a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail. The FPGA system power control block is configured to coordinate and execute a transfer of required communications between the FPGA and the host power management integrated circuit.
1. An FPGA power management system comprising:
a host power management integrated circuit connected to a system power control block of an FPGA via an FPGA configuration/monitoring bus and a computing device via a power configuration/monitoring bus;
the host power management integrated circuit comprising:
a configuration and monitoring block configured to communicate configuration/monitoring signals to and from the FPGA system power control block and the computing device;
at least one voltage regulator for supplying an output voltage to an FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block;
a power profiler configured to measure and supply to the configuration and monitoring block an output current on the FPGA power rail;
the FPGA system power control block configured to coordinate and execute a transfer of required communications between the FPGA and the host power management integrated circuit; and
the computing device comprising a display and an input device for monitoring and controlling of an aspect of FPGA operation, and FPGA design tools and power design tools for altering FPGA configuration or power;
wherein the monitoring of an aspect of the FPGA operation comprises monitoring of dynamic and average current consumption on the FPGA power rail; and
wherein the controlling of an aspect of the FPGA operation comprises altering of the FPGA configuration or power with said FPGA design tools and power design tools, based upon said monitoring, in a co-design aspect, to optimize at least one of the following FPGA operation parameters: thermal needs, thermal dissipation, power needs, power losses, power generation, execution speed, power, configuration and energy efficiency.
2. The FPGA power management system according to claim 1 , wherein the power profiler is further configured to supply cycle-by-cycle dynamic current measurements and average currents to the configuration and monitoring block.
3. The FPGA power management according to claim 1 , wherein the power configuration/monitoring bus is configured to communicate relevant data for purposes of monitoring and co-design.
4. The FPGA power management according to claim 3 , wherein the relevant data comprises current measurements.
5. The FPGA power management according to claim 1 , wherein the host power management integrated circuit further comprises a host controller connected to the power configuration/monitoring bus and configured to control a slave power management integrated circuit via a slave communication bus.
6. The FPGA power management system according to claim 5 , wherein the slave power management integrated circuit comprises a slave configuration and monitoring block;
at least one voltage regulator for supplying an output voltage to another FPGA power rail according to a power configuration signal communicated by the configuration and monitoring block; and
a slave power profiler configured to measure and supply to the configuration and monitoring block an output current on the other FPGA power rail.
7. The FPGA power management system according to claim 6 , wherein the host power management integrated circuit is based on a mixed-signal process and the slave power management integrated circuit is based on an analog process.
8. The FPGA power management system according to claim 7 , wherein the analog process is a Bipolar process.
9. The FPGA power management system according to claim 1 , wherein the system power control block of the FPGA is a soft block or a hard block.
10. The FPGA power management system according to claim 1 adjustable to firmware upgrades.
11. The FPGA power management system according to claim 1 , wherein the system power control block of the FPGA is configured to provide a power demand forecast to the host power management integrated circuit and wherein the host power management integrated circuit is configured to adjust power levels to actual needs ahead of time.
12. The FPGA power management system according to claim 1 , wherein the computing device is configured to execute code that may guide a user by displaying prompts and suggested values for configuration of the FPGA and voltage regulator in order to optimize a system parameter.
13. The FPGA power management system according to claim 12 , wherein the system parameter comprises power losses or thermal dissipation.
14. The FPGA power management system according to claim 1 , wherein the computing device is configured to execute code that adjusts the configuration of the FPGA and power controllers automatically.