IP Library Granted Patent US 10,068,875
Granted Patent B2
US 10,068,875 · App. 14/920,394 · Granted Sep 4, 2018

Apparatuses and methods for heat transfer from packaged semiconductor die

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Quick Facts
Patent No.
US 10,068,875
App. No.
14/920,394
Granted
Sep 4, 2018
Kind
B2
Abstract

Apparatuses and methods for heat transfer from packaged semiconductor die are described. For example, an apparatus may include a plurality of die in a stack, and a barrier in close proximity to at least an edge of each of the plurality of die. The apparatus may further include fill material in spaces between adjacent die of the plurality of die and in between the plurality of die and the barrier.

Claims (37)

1. An apparatus, comprising:

a substrate;

a logic die on the substrate;

a plurality of memory dies in a stack on the logic die;

a barrier in close proximity to at least an edge of each of the plurality of memory dies and supported, at least in part, by the substrate and the logic die;

a fill material in spaces between adjacent dies of the plurality of memory dies and in between the plurality of memory dies and the barrier, the fill material disposed continuously from at least an edge of a memory die of the plurality of memory dies to at least another edge of another memory die of the plurality of memory dies, the edge of the memory die facing a first side of the barrier, and the other edge of the memory die facing the first side of the barrier, wherein the barrier encloses the fill material; and

a thermal interface material disposed over a top and a second side of the barrier, the thermal interface material also being disposed partly between an edge of at least one memory die of the plurality of memory die, the at least one memory die facing the first side of the barrier.

2. The apparatus of claim 1 , wherein the logic die supports the plurality of memory dies and at least a portion of the barrier.

3. The apparatus of claim 2 , wherein a portion of the barrier not supported by the logic die is supported by the substrate.

4. The apparatus of claim 3 , wherein the barrier encircles the plurality of memory dies, and wherein the barrier is in close proximity to edges of each of the plurality of memory dies.

5. The apparatus of claim 1 , wherein the barrier is a thermal electric cooler.

6. The apparatus of claim 1 , wherein each of the plurality of memory die are volatile memory, non-volatile memory, or combinations thereof.

7. The apparatus of claim 1 , wherein the barrier is configured to limit wicking of the fill material from the spaces between adjacent die of the plurality of memory die.

8. An apparatus, comprising:

a first die;

a plurality of second dies including a top die, wherein the first die and the plurality of second dies are arranged in a stack such that the first die supports the plurality of second dies; and

a barrier formed on at least a portion of the first die and adjacent to the plurality of second dies, wherein the barrier limits an amount of a fill material wicking from spaces between the plurality of second dies; and

a thermal interface material disposed over a top and a first side of the barrier, the thermal interface material also being disposed partly between an edge of the top die facing a second side of the barrier.

9. The apparatus of claim 8 , wherein the barrier encircles the plurality of second dies, and wherein some of the fill material fills a space between an edge of the plurality of second dies and the barrier.

10. The apparatus of claim 9 , wherein the barrier is formed from a plurality of thermoelectric coolers.

11. The apparatus of claim 10 , wherein a number of the plurality of thermoelectric coolers enabled is variable.

12. The apparatus of claim 11 , wherein the number of the plurality of thermoelectric cooler is configured to be enabled based on a temperature of at least the first die.

13. The apparatus of claim 11 , wherein the number of the plurality of thermoelectric cooler is configured to be enabled based on a level of power consumption of at least the first die.

14. The apparatus of claim 8 , wherein the first die is a logic die and the plurality of second dies is a plurality of memory dies.

15. The apparatus of claim 8 , wherein a substrate supports the first die, the plurality of second dies, and the barrier, and a lid coupled to the substrate and configured to enclose the first die, the plurality of second dies, and the barrier.

16. The apparatus of claim 8 , wherein the areas that are not filled with the fill material include an exposed area between the side of the top die and over the barrier, and wherein the areas that are not filled with the fill material further include an exposed area above the top die and below a lid of the apparatus.

17. An apparatus, comprising:

a plurality of dies arranged in a stack on a substrate, wherein adjacent dies in the plurality of dies are separated by respective spaces;

a barrier formed, at least in part, on the substrate, to encircle the plurality of dies, formed on a bottom die of the plurality of dies, and in close proximity to edges of each of the plurality of dies;

a fill material in the respective spaces and between the edge of at least one die of the plurality of dies and the barrier, the fill material disposed between a first side of the barrier and an edge of the at least one die of the plurality of dies, the edge of the at least one die facing the first side of the barrier, wherein the barrier encloses the fill material; and

a thermal interface material disposed over a top and a second side of the barrier, the thermal interface material also being disposed partly between an edge of a die of the plurality of dies, the edge of the die facing the first side of the barrier.

18. The apparatus of claim 17 , wherein the length or width of the bottom die of the plurality of dies is larger than any other corresponding length or corresponding width of any die of the plurality of dies.

19. The apparatus of claim 17 , wherein at least a first portion of the barrier is supported by the bottom die.

20. The apparatus of claim 19 , wherein a second portion of the barrier is supported by the substrate, wherein the substrate is attached to the bottom die.

21. The apparatus of claim 17 , wherein the barrier comprises a material of high thermal conductivity.

22. The apparatus of claim 21 , wherein the material is a metal or a non-metallic material.

23. The apparatus of claim 17 , wherein the barrier is configured to limit an amount of the fill material pooling from spaces between the plurality of dies.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2015
From: HEMBREE, DAVID R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 036859/0631 →