IP Library Granted Patent US 9,608,091
Granted Patent B2
US 9,608,091 · App. 14/921,445 · Granted Mar 28, 2017

Method for manufacturing a semiconductor device

Inventor: Tatsuyoshi Mihara (Tokyo, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L29/66833G11C11/5671G11C16/0475H01L27/1104H01L27/11568H01L29/4234H01L29/792H01L21/823468H01L27/0629H01L29/66545
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Quick Facts
Patent No.
US 9,608,091
App. No.
14/921,445
Granted
Mar 28, 2017
Kind
B2
Abstract

The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

Claims (15)

1. A method for manufacturing a semiconductor device, comprising the steps of:

(a) providing a semiconductor substrate having a main surface, the main surface including a first region for a MISFET of a memory cell and a second region for a capacitive element;

(b) forming a first conductor film over the main surface of the semiconductor substrate in the first and second regions via a first insulation film;

(c) after the step (b), patterning the first conductor film to form a first gate electrode of the MISFET in the first region and a first electrode of the capacitive element in the second region, the first electrode having a first pattern and a second pattern which are opposed to each other in a sectional view;

(d) after the step (c), forming a second insulation film so as to cover a side surface of the first gate electrode of the MISFET and side surfaces of the first and second patterns of the first electrode; and

(e) after the step (d), forming a second conductor film over the main surface of the semiconductor substrate in the first and second regions, thereby to form a second gate electrode of the MISFET on a surface of the second insulation film and a second electrode of the capacitive element at a space between the first and the second patterns with the second insulation film in the sectional view.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:

(f) after the step (e), removing the second conductor film over the first gate electrode in the first region and the first electrode in the second region, and leaving the second conductor film with the second insulation film so as to fill the space between the first and the second patterns in the sectional view.

3. The method for manufacturing a semiconductor device according to claim 1 ,

wherein in the step (d), the second insulation film includes a first silicon oxide film, a silicon nitride film and a second silicon oxide film, and

wherein the silicon nitride film is formed between the first silicon oxide film and the second silicon oxide film.

4. The method for manufacturing a semiconductor device according to claim 2 ,

wherein in the step (b), a third insulation film is formed over the first conductor film in the first and the second region.

5. The method for manufacturing a semiconductor device according to claim 4 ,

wherein in the step (f), an upper surface of the second conductor film between the first and the second patterns is higher than an upper surface of the first electrode.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2012-194420 · Sep 4, 2012 · national
Continuity (3)
Continuation 14466092 · Aug 22, 2014
Continuation 13964576 · Aug 12, 2013
Related Publication 20160043200A1 · Feb 11, 2016