Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry can include a sense amplifier coupled to a pair of complementary sense lines and a compute component coupled to the sense amplifier via pass gates coupled to logical operation selection logic. The logical operation selection logic can be configured to control pass gates based on a selected logical operation.
1. An apparatus, comprising:
an array of memory cells; and
sensing circuitry coupled to the array, and comprising:
a sense amplifier coupled to a pair of complementary sense lines; and
a compute component coupled to the sense amplifier via a pair of pass gates and a pair of swap gates coupled to logical operation selection logic,
wherein the logical operation selection logic is configured to control the pair of pass gates and the pair of swap gates based on a selected logical operation;
wherein the pair of pass gates are configured to be enabled to transfer signals on the pair of complementary sense lines to a first node and a second node of a compute component latch in an un-transposed manner;
wherein the pair of swap gates are configured to be enabled to transfer signals on the pair of complementary sense lines to the first node and the second node of the compute component latch in a transposed manner; and
wherein which one of the pair of pass gates and the pair of swap gates are enabled in association with performing the selected logical operation depends on:
a status of control signals provided to the logical operation selection logic and corresponding to the selected logical operation; and
a data value stored in the compute component latch.
2. The apparatus of claim 1 , wherein the sensing circuitry is configured to initially store a result of the selected logical operation in the compute component in response to control signals corresponding to the selected logical operation being provided to the logical operation selection logic after the sense amplifier is enabled.
3. The apparatus of claim 1 , wherein the sensing circuitry is configured to initially store a result of the selected logical operation in the sense amplifier in response to control signals corresponding to the selected logical operation being provided to the logical operation selection logic before the sense amplifier is enabled.
4. The apparatus of claim 1 , wherein the sensing circuitry is configured to implement an XOR as the selected logical operation responsive to:
the status of the control signals provided to the logical operation selection logic being a first status; and
the data value stored in the compute component latch being a particular data value.
5. The apparatus of claim 4 , wherein the sensing circuitry is configured to implement an XNOR as the selected logical operation responsive to:
the status of the control signals provided to the logical operation selection logic being a different status; and
the data value stored in the compute component latch being a different particular data value.
6. The apparatus of claim 1 , wherein the sensing circuitry is configured to perform the logical operation without transferring data via an input/output (I/O) line.
7. The apparatus of claim 1 , wherein a gate of the pair of pass gates are coupled together and a gate of the pair of swap gates are coupled together.
8. An apparatus, comprising:
an array of memory cells; and
sensing circuitry coupled to the array and comprising:
a sense amplifier coupled to a pair of complementary sense lines; and
a compute component coupled to the sense amplifier via a pair of pass gates and a pair of swap gates; and
logical operation selection logic controlled to perform a selected logical operation from among a plurality of logical operations based on a status of one or more logic selection control signals;
wherein the logical operation selection logic is configured to control the pair of pass gates and the pair of swap gates based on the selected logical operation;
wherein the pair of pass gates are configured to be enabled to transfer signals on the pair of complementary sense lines to a first node and a second node of a compute component latch in an un-transposed manner;
wherein the pair of swap gates are configured to be enabled to transfer signals on the pair of complementary sense lines to the first node and the second node of the compute component latch in a transposed manner; and
wherein which one of the pair of pass gates and the pair of swap gates are enabled in association with performing the selected logical operation depends on:
the status of the one or more logic selection control signals and corresponding to the selected logical operation; and
a data value stored in the compute component latch.
9. The apparatus of claim 8 , wherein the compute component comprises a loadable shift register configured to shift a data value to an adjacent compute component.
10. The apparatus of claim 8 , further comprising a controller configured to control the sensing circuitry to determine a result of the logical operation based on a first data value stored in the sense amplifier and a second data value stored in the compute component.
11. The apparatus of claim 10 , wherein the controller is configured to control the sensing circuitry to selectably store the result of the logical operation in one of the sense amplifier and the compute component based on the one or more logic selection control signals.
12. The apparatus of claim 11 , wherein the controller is configured to control the sensing circuitry to initially store the result of the logical operation in the compute component by providing the one or more logic selection control signals corresponding to the selected logical operation to the logical operation selection logic after the sense amplifier is enabled.
13. The apparatus of claim 11 , wherein the controller is configured to control the sensing circuitry to initially store the result of the logical operation in the sense amplifier by providing the one or more logic selection control signals corresponding to the selected logical operation to the logical operation selection logic before the sense amplifier is enabled.
14. The apparatus of claim 8 , wherein the sensing circuitry comprises transistors formed on pitch with the memory cells.
15. The apparatus of claim 8 , wherein a gate of the pair of pass gates are coupled together and a gate of the pair of swap gates are coupled together.
16. An apparatus, comprising:
an array of memory cells; and
sensing circuitry coupled to the array via a pair of complementary sense lines, the sensing circuitry comprising:
a sense amplifier coupled to the pair of complementary sense lines; and
a compute component comprising a compute component latch selectably coupled to the pair of complementary sense lines via operation of a pair of pass gates and a pair of swap gates; and
logical operation selection logic controlled to perform a selected logical operation to be implemented by the sensing circuitry from among a plurality of logical operations based on a status of one or more logic selection control signals;
wherein the logical operation selection logic is configured to control the pair of pass gates and the pair of swap gates based on the selected logical operation;
wherein the pair of pass gates are configured to be enabled to transfer signals on the pair of complementary sense lines to a first node and a second node of the compute component latch in an un-transposed manner;
wherein the pair of swap gates are configured to be enabled to transfer signals on the pair of complementary sense lines to the first node and the second node of the compute component latch in a transposed manner; and
wherein which one of the pair of pass gates and the pair of swap gates are enabled in association with performing the selected logical operation depends on:
the status of the one or more logic selection control signals and corresponding to the selected logical operation; and
a data value stored in the compute component latch.
17. The apparatus of claim 16 , wherein logical operation selection logic comprises:
a first transistor coupled to a first one of the one or more logic selection control signals and to a common gate of the pair of swap gates;
a second transistor coupled to a second one of the one or more logic selection control signals and to a common gate of the pair of pass gates;
a third transistor coupled to a third one of the one or more logic selection control signals and to the common gate of the pair of pass gates; and
a fourth transistor coupled to a fourth one of the one or more logic selection control signals and to the common gate of the pair of swap gates,
wherein a gate common to the first and second transistors is coupled to a first one of the pair of complementary sense lines, and a gate common to the third and fourth transistors is coupled to a second one of the pair of complementary sense lines.
18. The apparatus of claim 16 , wherein a gate of the pair of pass gates are coupled together and a gate of the pair of swap gates are coupled together.
19. A method, comprising:
loading a first data value to a compute component latch of a sensing circuitry coupled to an array of memory cells via a pair of complementary sense lines;
performing a selected logical operation on the first data value and a second data value by:
providing, to logical operation selection logic, control signals corresponding to the selected logical operation; and
enabling a sense amplifier coupled to the compute component via the pair of complementary sense lines to sense the second data value;
wherein the compute component latch is coupled to the sense amplifier via a pair of pass gates and a pair of swap gates coupled to logical operation selection logic;
wherein the logical operation selection logic is configured to control the pair of pass gates and the pair of swap gates based on a selected logical operation;
wherein the pair of pass gates are configured to be enabled to transfer signals on the pair of complementary sense lines to a first node and a second node of a compute component latch in an un-transposed manner;
wherein the pair of swap gates are configured to be enabled to transfer signals on the pair of complementary sense lines to the first node and the second node of the compute component latch in a transposed manner; and
wherein which one of the pair of pass gates and the pair of swap gates are enabled in association with performing the selected logical operation depends on:
a status of the control signals provided to the logical operation selection logic and corresponding to the selected logical operation; and
a data value stored in the compute component latch.
20. The method of claim 19 , wherein the method includes:
initially storing a result of the selected logical operation in the compute component responsive to providing the control signals corresponding to the selected logical operation after enabling the sense amplifier in association with sensing the second data value; and
initially storing the result of the selected logical operation in the sense amplifier responsive to providing the control signals corresponding to the selected logical operation before enabling the sense amplifier in association with sensing the second data value.
21. The method of claim 19 , wherein loading the first data value to the compute component comprises loading the first data value from a memory cell coupled to the pair of complementary sense lines and to an access line of the array.
22. The method of claim 21 , further comprising sensing the second data value from a different memory cell coupled to the pair of complementary sense lines and to a different access line of the array.
23. The method of claim 19 , wherein loading the first data value to the compute component includes storing the first data value to a loadable shift register configured to shift bidirectionally.
24. The method of claim 19 , wherein the selected logical operation comprises an XOR logical operation.
25. The method of claim 19 , wherein the selected logical operation comprises an XNOR logical operation.
26. The method of claim 19 , further comprising determining a result of the logical operation using the sensing circuitry without transferring data to a control component external to the array of memory cells.