SEMICONDUCTOR DEVICE
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
1 . A semiconductor device, comprising:
a first interlayer insulating layer including a first trench, on a substrate;
a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart; and
a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
2 . The semiconductor device of claim 1 , wherein at a point where the first liner layer and the top surface of the first metal wire are adjacent to each other, an uppermost surface of the first liner layer and the top surface of the first metal wire are continuous.
3 . The semiconductor device of claim 2 , wherein at the point where the first liner layer and the top surface of the first metal wire are adjacent to each other, no step is formed between the uppermost surface of the first liner layer and the top surface of the first metal wire.
4 . (canceled)
5 . (canceled)
6 . The semiconductor device of claim 1 , wherein the top surface of the first metal wire comprises a first point and a second point,
a distance up to the first point from a point where the top surface of the first metal wire and the uppermost surface of the first liner layer meet is less than a distance up to the second point from the point where the top surface of the first metal wire and the uppermost surface of the first liner layer meet, and
a depth up to the first point from the uppermost surface of the first liner layer is less than a depth up to the second point from the uppermost surface of the first liner layer.
7 . The semiconductor device of claim 1 , wherein the noble metal comprises at least one of ruthenium (Ru), platinum (Pt), iridium (Ir), and rhodium (Rh).
8 .- 10 . (canceled)
11 . The semiconductor device of claim 1 , further comprising:
a capping layer formed on the top surface of the first metal wire.
12 . The semiconductor device of claim 11 , wherein the capping layer directly contacts the first liner layer and the first metal wire.
13 . (canceled)
14 . (canceled)
15 . The semiconductor device of claim 11 , wherein the capping layer does not extend on the top surface of the first interlayer insulating layer.
16 . (canceled)
17 . The semiconductor device of claim 11 , wherein the capping layer comprises at least one of cobalt (Co), ruthenium (Ru), and manganese (Mn).
18 . The semiconductor device of claim 1 , further comprising:
a first barrier layer formed along the side wall and the bottom surface of the first trench, between the first interlayer insulating layer and the first liner layer.
19 . (canceled)
20 . (canceled)
21 . The semiconductor device of claim 1 , further comprising:
a second interlayer insulating layer comprising a second trench, on the first interlayer insulating layer;
a second liner layer formed along a side wall and a bottom surface of the second trench and including the noble metal; and
a second metal wire filling the second trench and electrically connected with the first metal wire,
wherein a top surface of the second metal wire has a convex shape toward the bottom surface of the second trench.
22 .- 25 . (canceled)
26 . A semiconductor device, comprising:
an interlayer insulating layer including a trench, on a substrate;
a first liner layer formed along a side wall and a bottom surface of the trench;
a metal wire filling the trench and comprising copper (Cu), on the first liner layer, a top surface of the metal wire having a convex shape toward the bottom surface of the trench; and
a second liner layer including a first part formed along the side wall and the bottom surface of the metal wire and a second part formed along the top surface of the metal wire, the second liner covering the metal wire,
wherein one of the first liner layer and the second liner layer comprises a noble metal that belongs to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPA) and belongs to one of eighth to tenth groups of the periodic chart.
27 . The semiconductor device of claim 26 , wherein the first part of the second liner layer is disposed between the first liner layer and the metal wire, and
the noble metal is in the first part of the second liner layer.
28 . The semiconductor device of claim 27 , wherein the first part of the second liner layer directly contacts the metal wire, and
no step is formed between an uppermost surface of the first part of the second liner layer and the top surface of the metal wire.
29 . (canceled)
30 . The semiconductor device of claim 26 , wherein the first liner layer is disposed between the first part of the second liner layer and the metal wire, and
the noble metal is in the first liner layer.
31 . The semiconductor device of claim 30 , wherein the first liner layer and the metal wire directly contact each other, and
no step is formed between the uppermost surface of the first liner layer and the top surface of the metal wire.
32 . (canceled)
33 . (canceled)
34 . A semiconductor device, comprising:
an interlayer insulating layer comprising a trench, on a substrate;
a barrier layer formed along a side wall and a bottom surface of the trench;
a ruthenium (Ru) liner layer formed along the side wall and the bottom surface of the trench, on the barrier layer;
a metal wire filling the trench and comprising copper, on the ruthenium liner layer, a top surface of the metal wire having a convex shape toward the bottom surface of the trench and being continuous with an uppermost surface of the ruthenium liner layer; and
a capping layer formed along the top surface of the metal wire.
35 . The semiconductor device of claim 34 , wherein the metal wire directly contacts the liner layer, and
no step is formed between the uppermost surface of the liner layer and the top surface of the metal wire.
36 . The semiconductor device of claim 34 , wherein the capping layer is a cobalt (Co) layer.
37 . (canceled)
38 . (canceled)
39 . The semiconductor device of claim 34 , wherein the interlayer insulating layer comprises a low-dielectric material having a lower dielectric constant than silicon oxide.
40 .- 57 . (canceled)