Method for fabricating self-aligned contact in a semiconductor device
A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.
1. A semiconductor device comprising:
a gate structure disposed over a substrate;
a source/drain region; and
sidewall spacers disposed on both side walls of the gate structure, wherein:
the sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure,
the second space layer includes a lateral portion laterally extending over the source/drain region and partially covering the source/drain region, and
the lateral portion separates the third and fourth spacer layers from the source/drain region.
2. The semiconductor device of claim 1 , wherein:
the first, third and fourth spacer layers are made of a silicon-nitride based material, and
the second spacer layer is made of a silicon-oxide based material.
3. The semiconductor device of claim 2 , wherein the silicon-nitride based material includes SiN, SiCN, SiON or SiOCN, and the silicon-oxide based material includes silicon oxide.
4. The semiconductor device of claim 2 , wherein the first spacer layer is made of SiCN.
5. The semiconductor device of claim 2 , wherein the fourth spacer layer is made of SiN.
6. The semiconductor device of claim 2 , wherein the third spacer layer is made of SiCN or SiN.
7. The semiconductor device of claim 2 , wherein the third spacer layer is made of a different material than the fourth spacer layer.
8. The semiconductor device of claim 1 , further comprising:
a contact plug in contact with a part of the source/drain region,
wherein the fourth spacer layer is in contact with the contact plug.
9. The semiconductor device of claim 8 , wherein bottoms of the third and fourth spacer layers are located above the source/drain regions.
10. The semiconductor device of claim 1 , wherein the gate structure comprises:
a gate dielectric layer;
a gate electrode layer disposed over the gate dielectric layer; and
a cap layer made of an insulating material disposed over the gate electrode,
wherein a height of the sidewall spacers is substantially the same as a height of the cap layer.
11. A method of manufacturing a semiconductor device, the method comprising:
forming a gate structure over a substrate;
forming a first sidewall spacer layer on a sidewall of the gate structure;
forming an oxide layer, as a second sidewall spacer layer, on the first sidewall spacer layer;
forming a third sidewall spacer layer on the second sidewall spacer layer; and
forming a contact etching stop layer on the third sidewall spacer layer and the substrate, wherein:
the forming the first sidewall spacer layer includes forming a lower layer and forming an upper layer over the lower layer, and
between the forming the lower layer and the forming the upper layer over the lower layer, ion implantation is performed through the lower layer.
12. The method of claim 11 , wherein:
the first, third and fourth spacer layers are made of SiN, SiCN, SiON or SiOCN.
13. The method of claim 11 , further comprising, after forming the fourth sidewall spacer layer:
forming an interlayer dielectric layer over the gate structure with the first to fourth spacer layers;
forming a contact hole in the interlayer dielectric layer by using the contact etch stop layer as an etching stop layer;
removing the contact etch stop layer in the contact hole; and
filling the contact hole with a conductive material.
14. The method of claim 11 , wherein the oxide layer is formed by oxidizing the first sidewall spacer layer.
15. The method of claim 11 , wherein:
the gate structure is a dummy gate structure, and
the method further comprises, after forming the fourth sidewall spacer layer:
forming an interlayer dielectric layer over the dummy gate structure with the first to fourth spacer layers;
removing the dummy gate structures to form a gate opening; and
forming a metal gate structure including a metal gate electrode layer disposed over a high-k gate dielectric layer in the opening.
16. The method of claim 15 , further comprising, after forming the metal gate structure:
recessing the metal gate electrode layer; and
forming a cap layer over the recessed gate electrode layer.
17. The method of claim 11 , further comprising forming a source/drain region including a strain material having a different lattice constant from a channel region,
wherein bottom of the third spacer layer is located above the source/drain region.
18. A method of manufacturing a semiconductor device, the method comprising:
forming a first dummy gate structure for an n-channel transistor with a mask layer disposed thereon over a substrate;
forming a first insulating layer over the first dummy gate structure;
implanting first ions through the first insulating layer for the n-channel transistor;
forming a second insulating layer over the first insulating layer;
forming a third insulating layer over the second insulating layer;
etching the first to third insulating layers thereby forming a first n-sidewall spacer layer on a side wall of the first dummy gate structure;
forming a first source/drain structure in the substrate on a side portion of the first n-sidewall spacer;
after forming the first source/drain structure, removing the third insulating layer from the first n-sidewall spacer layer;
forming an oxide layer, as a second sidewall spacer layer, on the first n-sidewall spacer layer;
forming a third n-sidewall spacer layer on the second sidewall spacer layer; and
forming a contact etching stop layer on the n-third sidewall spacer layer and the substrate.
19. The method of claim 18 , further comprising:
forming a second dummy gate structure for a p-channel transistor with a mask layer disposed thereon over the substrate;
forming the first insulating layer over the second dummy gate structure;
implanting second ions through the first insulating layers for the for the p-channel transistor;
forming the second insulating layer over the first insulating layer;
forming the third insulating layer over the second insulating layer;
after forming the third insulating layer, removing the third insulating layer;
forming a fourth insulating layer over the second insulating layer after removing the third insulating layer;
etching the first, second and fourth insulating layer thereby forming a first p-sidewall spacer layer on a side wall of the second dummy gate structure;
forming a second source/drain structure in the substrate on a side portion of the first p-sidewall spacer;
after forming the second source/drain structure, removing the fourth insulating layer from the first p-sidewall spacer layer;
forming an oxide layer on the first p-sidewall spacer layer;
forming a third p-sidewall spacer layer on the oxide layer; and
forming a contact etching stop layer on the third p-sidewall spacer layer and the substrate.
20. The method of claim 11 , further comprising forming a source/drain region, wherein:
the oxide layer is formed such that the oxide layer has a lateral portion laterally extending over the source/drain region and covering the source/drain region, and
the lateral portion separates the third spacer layer and the contact etching stop layer from the source/drain region.