IP Library › Granted Patent US 9,952,973
Granted Patent B2
US 9,952,973 · App. 14/927,410 · Granted Apr 24, 2018

Reducing write-backs to memory by controlling the age of cache lines in lower level cache

Inventor: Md Kamruzzaman (Cupertino, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0833G06F12/0804G06F12/0806G06F12/122G06F12/123G06F12/128G06F12/12G06F2212/1016G06F2212/1021G06F2212/621
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Quick Facts
Patent No.
US 9,952,973
App. No.
14/927,410
Granted
Apr 24, 2018
Kind
B2
Abstract

A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.

Claims (20)

1. A method for reducing write-backs to memory, comprising:

determining whether a read request entering a lower level cache is directed to a clean cache line without modified data;

responsive to determining that the read request is directed to the clean cache line, maintaining an age information of the clean cache line by not updating the age information of the clean cache line to reduce a number of write-backs to memory;

determining whether the read request entering the lower level cache is directed to a dirty cache line containing modified data;

responsive to determining that the read request is directed to the dirty cache line containing modified data, updating an age information of the dirty cache line; and

responsive to determining that the read request is not present in the lower level cache, evicting a least recently used cache line from a plurality of non-updated age information clean cache lines and a plurality of updated age information dirty cache lines.

2. A system, comprising:

a processor; and

a memory storing program code, which, when executed on the processor, performs an operation for managing memory, the operation comprising:

determining whether a read request entering a lower level cache is directed to a clean cache line without modified data;

responsive to determining that the read request is directed to the clean cache line, maintaining an age information of the clean cache line by not updating the age information of the clean cache line to reduce a number of write-backs to memory;

determining whether the read request entering the lower level cache is directed to a dirty cache line containing modified data;

responsive to determining that the read request is directed to the dirty cache line containing modified data, updating an age information of the dirty cache line; and

responsive to determining that the read request is not present in the lower level cache, evicting a least recently used cache line from a plurality of non-updated age information clean cache lines and a plurality of updated age information dirty cache lines.

3. A non-transitory computer readable storage medium having stored thereon instructions that when executed by a processor causes a processor to perform an operation for managing memory, comprising:

determining whether a read request entering a lower level cache is directed to a clean cache line without modified data;

responsive to determining that the read request is directed to the clean cache line, maintaining an age information of the clean cache line by not updating the age information of the clean cache line to reduce a number of write-backs to memory;

determining whether the read request entering the lower level cache is directed to a dirty cache line containing modified data;

responsive to determining that the read request is directed to the dirty cache line containing modified data, updating an age information of the dirty cache line; and

responsive to determining that the read request is not present in the lower level cache, evicting a least recently used cache line from a plurality of non-updated age information clean cache lines and a plurality of updated age information dirty cache lines.

Assignments (6)
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED ON REEL 036936 FRAME 0396. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 11, 2016
From: KAMRUZZAMAN, MD
To: HGST NETHERLANDS B.V.
Reel/Frame 039651/0864 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2015
From: KAMRUZZAMAN, MD
To: HGST NETHERLANDS B.V.
Reel/Frame 036936/0396 →
Continuity (1)
Related Publication 20170123984A1 · May 4, 2017