Granted Patent B2

US 10,347,637 · App. 14/927,721 · Granted Jul 9, 2019

Abstract

Claims (43)

1. A semiconductor device comprising:

a dynamic random access memory (DRAM) array comprising:

DRAM cells, each DRAM cell comprising a channel region comprising indium gallium zinc oxide, opposing ends of the channel region in direct contact with a metal material, a first DRAM cell of the DRAM cells supported by a material, a second DRAM cell of the DRAM cells positioned above the first DRAM cell of the DRAM cells, and a first channel material of the first DRAM cell perpendicular to a second channel material of the second DRAM cell.

2. A semiconductor device comprising:

a dynamic random access memory (DRAM) array comprising:

DRAM cells, each DRAM cell comprising a channel region comprising indium gallium zinc oxide, opposing ends of the channel region in direct contact with a metal material, and at least one DRAM cell of the DRAM cells comprising:

a transistor comprising the channel region comprising indium gallium zinc oxide; and

a capacitor comprising:

a bottom capacitor electrode configured to provide a drain region of the transistor.

3. The semiconductor device of claim 2 , wherein the channel region of each DRAM cell is oriented vertically relative to a surface of a material supporting the semiconductor device.

4. The semiconductor device of claim 2 , wherein the transistor is oriented vertically relative to a surface of a material on which the transistor is located.

5. The semiconductor device of claim 2 , further comprising an insulative material directly contacting sidewalls of the channel region.

6. The semiconductor device of claim 2 , further comprising another insulative material surrounding the channel region.

7. The semiconductor device of claim 5 , wherein an upper surface of the channel region is substantially coplanar with an upper surface of the insulative material.

8. The semiconductor device of claim 2 , wherein the capacitor further comprises a top capacitor electrode and a capacitor dielectric material between the bottom capacitor electrode and the top capacitor electrode.

9. The semiconductor device of claim 2 , wherein a first channel region of a first DRAM cell is parallel to a second channel region of a second DRAM cell.

10. The semiconductor device of claim 9 , further comprising a gate electrode in operative communication with the first channel region and the second channel region.

11. The semiconductor device of claim 9 , further comprising an additional metal material in contact with the first channel region and the second channel region.

12. A method of forming a semiconductor device comprising:

forming a dynamic random access memory (DRAM) array comprising DRAM cells, forming the DRAM cells comprising at least a first DRAM cell and at least a second DRAM cell, comprising:

forming a first transistor of the first DRAM cell comprising:

forming a source region supported by a material;

forming a gate electrode isolated within an insulative material above the source region;

forming an opening in the insulative material to expose at least a portion of each of the source region and the gate electrode; and

forming a first channel material comprising indium gallium zinc oxide in the opening at a temperature less than or equal to about 800 degrees Celsius to form a first channel region comprising indium gallium zinc oxide, opposing ends of the channel region in direct contact with a metal material; and

forming a first capacitor of the first DRAM cell in electrical connection with the channel material; and

forming the second DRAM cell positioned above the first DRAM cell comprising:

forming a second transistor of the second DRAM cell above the first capacitor, the second transistor comprising a second channel material perpendicular to the first channel material; and

forming a second capacitor of the second DRAM cell above the second transistor.

13. The method of claim 12 , wherein forming a first capacitor of the first DRAM cell comprises:

forming a bottom capacitor electrode over the first channel material;

forming a capacitor dielectric material over the bottom capacitor electrode; and

forming a top capacitor electrode over the capacitor dielectric material;

wherein the bottom capacitor electrode is integrated with a drain region of the first transistor.

14. A semiconductor device comprising:

a dynamic random access memory (DRAM) array comprising DRAM cells, each DRAM cell comprising:

a transistor comprising an indium gallium zinc oxide channel region isolated from a gate electrode by an insulative material; and

a capacitor in operative communication with the transistor, the capacitor comprising a bottom capacitor electrode, a top capacitor electrode, and a capacitor dielectric material between the bottom capacitor electrode and the top capacitor electrode and the bottom capacitor electrode of the capacitor configured to provide a drain region of the transistor.

15. The semiconductor device of claim 14 , wherein the bottom capacitor electrode of the capacitor is aligned with a length of the indium gallium zinc oxide channel region.

16. The semiconductor device of claim 14 , wherein the bottom capacitor electrode of the capacitor comprises segments in contact with a portion of the indium gallium zinc oxide channel region.

17. The semiconductor device of claim 14 , wherein a first DRAM cell of the DRAM cells occupies a horizontal plane also occupied by a second DRAM cell of the DRAM cells.

18. The semiconductor device of claim 14 , wherein the gate electrode comprises a single gate electrode.

19. The semiconductor device of claim 14 , wherein the gate electrode comprises an access line.

Assignments (7)