IP Library Granted Patent US 9,837,496
Granted Patent B2
US 9,837,496 · App. 14/930,628 · Granted Dec 5, 2017

Semiconductor device and method for manufacturing same

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Quick Facts
Patent No.
US 9,837,496
App. No.
14/930,628
Granted
Dec 5, 2017
Kind
B2
Abstract

A semiconductor device includes: a channel layer which is made of In p Al q Ga 1-p-q N (0≦p+q≦1, 0≦p, and 0≦q); a barrier layer which is formed on the channel layer and is made of In r Al s Ga 1-r-s N (0≦r+s≦1, 0≦r) having a bandgap larger than that of the channel layer; a diffusion suppression layer which is selectively formed on the barrier layer and is made of In t Al u Ga 1-t-u N (0≦t+u≦1, 0≦t, and s>u); a p-type conductive layer which is formed on the diffusion suppression layer and is made of In x Al y Ga 1-x-y N (0≦x+y≦1, 0≦x, and 0≦y) having p-type conductivity; and a gate electrode which is formed on the p-type conductive layer.

Claims (48)

1. A semiconductor device comprising:

a first semiconductor layer which is made of In p Al q Ga 1-p-q N (0≦p+q≦1, 0≦p, and 0≦q);

a second semiconductor layer disposed on the first semiconductor layer, and is made of In r Al s Ga 1-r-s N (0≦r+s≦1, 0≦r) having a bandgap larger than that of the first semiconductor layer;

a third semiconductor layer which is selectively disposed on the second semiconductor layer, and is made of In t Al u Ga 1-t-u N (0≦t+u≦1, 0≦t, and s>u);

a fourth semiconductor layer disposed on the third semiconductor layer, and is made of In x Al y Ga 1-x-y N (0≦x+y≦1, 0≦x, and 0≦y) having p-type conductivity;

a gate electrode disposed on the fourth semiconductor layer; and

a source electrode and a drain electrode which are disposed directly on the second semiconductor layer.

2. The semiconductor device of claim 1 ,

wherein the third semiconductor layer has a variation in an amount of a p-type dopant per unit length in a film thickness direction, smaller than a variation in the fourth semiconductor layer.

3. The semiconductor device of claim 1 ,

wherein the second semiconductor layer includes a recessed portion formed on an upper surface thereof, and

the third semiconductor layer is disposed to fill at least a part of the recessed portion when viewed in a stacking direction.

4. The semiconductor device of claim 3 ,

wherein the third semiconductor layer is disposed to fill the recessed portion when viewed in the stacking direction.

5. The semiconductor device of claim 3 ,

wherein the third semiconductor layer has a structure in which a layer made of Al a Ga 1-a N (0<a≦1) and a layer made of GaN are stacked.

6. The semiconductor device of claim 5 ,

wherein the layer made of Al a Ga 1-a N (0<a≦1) in the third semiconductor layer has an Si concentration which is equal to or greater than 1×10 18 /cm 3 .

7. The semiconductor device of claim 5 ,

wherein the layer made of GaN in the third semiconductor layer has an Si concentration which is equal to or greater than 1×10 18 /cm 3 .

8. The semiconductor device of claim 1 ,

wherein a p-type dopant of the fourth semiconductor layer is Mg, and

the second semiconductor layer has an Mg concentration which is equal to or smaller than 1×10 19 /cm 3 in a portion that is in contact with the third semiconductor layer, and

the third semiconductor layer has an Mg concentration which is equal to or smaller than 1×10 19 /cm 3 in a portion that is in contact with the second semiconductor layer.

9. The semiconductor device of claim 1 ,

wherein the third semiconductor layer is made of GaN.

10. The semiconductor device of claim 1 ,

wherein the third semiconductor layer has an Si concentration which is equal to or greater than 1×10 18 /cm 3 .

11. The semiconductor device of claim 1 ,

wherein the second semiconductor layer has an Si concentration which is equal to or greater than 1×10 18 /cm 3 .

12. The semiconductor device of claim 1 ,

wherein the second semiconductor layer is formed by layering a layer not doped with Si and disposed on a side being in contact with the first semiconductor layer and a layer having an Si concentration equal to or greater than 1×10 18 /cm 3 and disposed on a side being in contact with the source electrode and the drain electrode.

13. The semiconductor device of claim 1 ,

wherein the fourth semiconductor layer is made of GaN.

14. The semiconductor device of claim 1 ,

wherein the fourth semiconductor layer is made of Al z Ga 1-z N (0<z≦1).

15. The semiconductor device of claim 1 ,

wherein the fourth semiconductor layer has a structure in which a layer made of Al z Ga 1-z N (0<z≦1) and disposed on a side being in contact with the third semiconductor layer and a layer made of GaN and disposed on a side being in contact with a gate electrode are stacked together.

16. The semiconductor device of claim 1 , further comprising a substrate on which the first semiconductor layer is disposed.

17. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first semiconductor layer made of In p Al q Ga 1-p-q N (0≦p+q≦1, 0≦p, and 0≦q);

forming a second semiconductor layer made of In r Al s Ga 1-r-s N (0≦r+s≦1, 0≦r) having a bandgap larger than that of the first semiconductor layer, on the first semiconductor layer;

forming a third semiconductor layer made of In t Al u Ga 1-t-u N (0≦t+u≦1, 0≦t, and s>u) on the second semiconductor layer;

forming a fourth semiconductor layer made of In x Al y Ga 1-x-y N (0≦x+y≦1, 0≦x, and 0≦y) having p-type conductivity on the third semiconductor layer;

forming a gate electrode on the fourth semiconductor layer;

removing a region other than a region corresponding to the gate electrode, from the third semiconductor layer and the fourth semiconductor layer, after forming the fourth semiconductor layer; and

forming a source electrode and a drain electrode directly on the second semiconductor layer.

18. The method for manufacturing a semiconductor device of claim 17 , further comprising the step of forming a substrate on which the first semiconductor layer is disposed.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2025
From: INFINEON TECHNOLOGIES AUSTRIA AG
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 072853/0508 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2024
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC HOLDINGS CORPORATION
Reel/Frame 069503/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2015
From: KINOSHITA, YUSUKE; TAMURA, SATOSHI; UEDA, TETSUZO
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 037172/0881 →