Fin FET and method of fabricating same
View Patent ↗A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.
1. A semiconductor device comprising:
a substrate including a fin active region;
a device isolation film disposed on the substrate;
a first gate stack disposed on a first portion of the fin active region; and
a source/drain region disposed at a second portion of the fin active region,
wherein the device isolation film comprises a first portion located adjacent to the fin active region and below the first gate stack,
wherein an upper surface of the first portion of the fin active region located under the first gate stack is higher than an upper surface of the first portion of the device isolation film,
wherein the first gate stack covers the upper surface of the first portion of the device isolation film, covers the upper surface of the first portion of the fin active region and extends along two sidewalls of the first portion of the fin active region, and
wherein the upper surface of the first portion of the fin active region is lower than an upper surface of the second portion of the fin active region.
2. The semiconductor device of claim 1 , wherein the first portion of the device isolation film contacts the fin active region.
3. The semiconductor device of claim 1 , wherein, with respect to a vertical cross section taken parallel to a horizontal length direction of the gate stack, the fin active region protrudes from the upper surface of the device isolation film.
4. The semiconductor device of claim 1 , further comprising a second gate stack disposed on a third portion of the fin active region.
5. The semiconductor device of claim 4 , wherein the second portion of the fin active region is disposed between the first portion of the fin active region and the third portion of the fin active region.
6. The semiconductor device of claim 4 , wherein an upper surface of the third portion of the fin active region located under the second gate stack is lower than the upper surface of the second portion of the fin active region.
7. The semiconductor device of claim 1 , further comprising a gate insulating layer disposed on the fin active region.
8. The semiconductor device of claim 7 , wherein the first gate stack is disposed on the gate insulating layer.
9. The semiconductor device of claim 1 , further comprising:
a first spacer disposed on a first sidewall of the first gate stack; and
a second spacer disposed on a second sidewall of the first gate stack.
10. The semiconductor device of claim 1 , wherein a bottom surface of the first gate stack is lower than an upper surface of the source/drain region.