Systems, methods and devices for programming a multilevel resistive memory cell

1. A method of programming a memory device, comprising:

programming a resistive memory storage element from an intermediate resistance state to a higher resistance state or a lower resistance state at least in part by applying a plurality of electrical pulses having peak pulse amplitudes that sequentially ramp in a first direction when the resistive memory storage element is being programmed to the higher resistance state and sequentially ramp in an opposite second direction when the resistive memory storage element is being programmed to the lower resistance state,

wherein when programming the resistive memory storage element to the lower resistance state, programming comprises applying a forward-biased staircase pulse sequence having a first polarity, and wherein when programming the resistive memory storage element to the higher resistance state, programming comprises applying a reverse-biased staircase pulse sequence having a second polarity opposite from the first polarity.

2. The method of claim 1 , wherein programming the resistive storage element comprises programming from the intermediate resistive state to the lower resistance state by applying the forward-biased staircase pulse sequence in which the peak amplitudes of the electrical pulses sequentially fall.

3. The method of claim 1 , wherein programming the resistive storage element comprises programming from the intermediate resistance state to the high resistance state by applying the reverse-biased staircase pulse sequence in which the peak amplitudes of the electrical pulses sequentially rise.

4. The method of claim 1 , wherein the resistive storage element comprises a phase change material, and wherein programming from the intermediate resistance state to the higher resistance state comprises at least partially amorphizing the phase change material, and wherein programming from the intermediate state to the lower resistance state comprises at least partially crystallizing the phase change material.

5. A method of programming a memory device, comprising:

programming a resistive memory storage element from an intermediate resistance state to a higher resistance state or a lower resistance state at least in part by applying a plurality of electrical pulses having peak pulse amplitudes that sequentially ramp in a first direction when the resistive memory storage element is being programmed to the higher resistance state and sequentially ramp in an opposite second direction when the resistive memory storage element is being programmed to the lower resistance state; and

after programming the resistive memory storage element to one of the higher resistance state or the lower resistance state, further programming the resistive memory storage element to the other one of the higher resistance state or the lower resistance state by applying a plurality of additional electrical pulses having peak pulse amplitudes that sequentially ramp in the first direction when the resistive memory storage element is being further programmed to the higher resistance state and sequentially ramp in the second direction when the resistive memory storage element is being further programmed to the lower resistance state.

6. The method of claim 5 , wherein programming the resistive storage element comprises programming from the intermediate resistive state to the lower resistance state, and further programming comprises programming from the lower resistance to the higher resistance state by applying the plurality of additional electrical pulses in which the peak pulse amplitudes sequentially increase.

7. The method of claim 5 , wherein programming the resistive storage element comprises programming from the intermediate resistive state to the higher resistance state, and further programming comprises programming from the higher resistance state to the lower resistance state by applying the plurality of additional electrical pulses in which the peak pulse amplitudes sequentially decrease.

8. A method of programming a memory device, comprising:

programming a resistive memory storage element from an intermediate resistance state to a higher resistance state or a lower resistance state at least in part by applying a plurality of electrical pulses having peak pulse amplitudes that sequentially ramp in a first direction when the resistive memory storage element is being programmed to the higher resistance state and sequentially ramp in an opposite second direction when the resistive memory storage element is being programmed to the lower resistance state; and

after programming the resistive memory storage element to one of the higher resistance state or the lower resistance state, further programming the resistive memory storage element back to the intermediate resistance state by applying a plurality of additional electrical pulses in which peak pulse amplitudes sequentially ramps in an opposite direction compared to the plurality of electrical pulses used for programming.

9. A method of programming a memory device, comprising:

programming a resistive memory storage element between an intermediate resistance state and one of a higher resistance state or a lower resistance state at least in part by applying a plurality of electrical pulses sufficient to cause migration of atoms in one direction between electrodes of the resistive memory storage element when the resistive memory storage element is being programmed to the higher resistance state and cause migration of atoms in an opposite direction between the electrodes when the resistive memory storage element is being programmed to the lower resistance state,

wherein programming the resistive memory storage element comprises programming the storage element from the intermediate resistance state to the lower resistance state by applying the plurality of electrical pulses having a bias such that the atoms migrate away from one of the electrodes that is positively biased relative to another one of the electrodes.

10. The method of claim 9 , wherein the plurality of electrical pulses comprise peak amplitudes which sequentially increase or decrease.

11. A method of programming a memory device, comprising:

programming a resistive memory storage element between an intermediate resistance state and one of a higher resistance state or a lower resistance state at least in part by applying a plurality of electrical pulses sufficient to cause migration of atoms in one direction between electrodes of the resistive memory storage element when the resistive memory storage element is being programmed to the higher resistance state and cause migration of atoms in an opposite direction between the electrodes when the resistive memory storage element is being programmed to the lower resistance state, and

wherein programming the resistive memory storage element comprises programming the storage element from the intermediate resistance state to the higher resistance state by applying the plurality of electrical pulses having a bias such that the atoms migrate toward one of the electrodes that is positively biased relative to another one of the electrodes.

12. The method of claim 11 , wherein the resistive memory storage element comprises a chalcogenide material, and wherein the atoms are atoms of the chalcogenide material.

13. The method of claim 12 , wherein the chalcogenide material comprises Ge and Sb, and wherein the atoms include one or both of Ge and Sb.

14. An apparatus, comprising:

a memory array comprising a plurality of resistive storage elements, wherein at least one resistive storage element is configured to be programmed to an intermediate resistance state between a higher resistance state and a lower resistance state; and

a controller configured to cause programming of one or more resistive storage elements from the intermediate resistance state to the higher resistance state or the lower resistance state at least in part by applying a plurality of electrical pulses having peak pulse amplitudes that change in a first direction when the resistive memory storage element is being programmed to the higher resistance state and change in a second direction opposite to the first direction when the resistive memory storage element is being programmed to the lower resistance state,

wherein the controller is configured to program the resistive memory storage element from the intermediate resistance state to the lower resistance state by applying the plurality of forward-biased electrical pulses having a first polarity, and is further configured to program the resistive memory storage element from the intermediate resistance state to the higher resistance state by applying the plurality of reverse-biased electrical pulses having a second polarity opposite from the first polarity.

15. The apparatus of claim 14 , wherein each of the plurality of resistive storage elements comprises a chalcogenide material disposed between a pair of electrodes.

16. The apparatus of claim 15 , wherein the controller is configured to cause programming of the one or more resistive storage elements by applying the one or more electrical pulses whose amplitudes are sufficient to cause migration of atoms of the chalcogenide material between the electrodes.

17. The apparatus of claim 16 , wherein the controller is configured to program the resistive memory storage element from the initial intermediate resistance state to the lower resistance state by applying the plurality electrical pulses having a bias such that the atoms migrate away from one of the electrodes that is positively biased relative to the other one of the electrodes.

18. The apparatus of claim 16 , wherein the controller is configured to program the resistive memory storage element from the initial intermediate resistance state to the higher resistance state by applying the plurality of electrical pulses having a bias such that the atoms migrate towards one of the electrodes that is positively biased relative to the other one of the electrodes.