Anti-eclipse circuitry with tracking of floating diffusion reset level
Imagers and associated devices and systems are disclosed herein. In one embodiment, an imager includes a pixel array and control circuitry operably coupled to the pixel array. The pixel array includes an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal. The control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.
1. An imager, comprising:
a pixel array including an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal; and
control circuitry operably coupled to the pixel array,
wherein the control circuitry includes an anti-eclipse circuit and a current mirror operably coupling the anti-eclipse circuit to the non-imaging pixel, and
wherein the control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.
2. The imager of claim 1 , further comprising a sample-and-hold circuit configured to sample and hold a voltage signal corresponding to the nominal reset signal.
3. The imager of claim 1 wherein the non-imaging pixel includes an imaging pixel that is shielded from incident light.
4. The imager of claim 1 wherein each of the imaging and non-imaging pixels includes:
a light sensitive element;
a floating diffusion node; and
a transfer transistor switchably coupling the light-sensitive element to the floating diffusion node.
5. The imager of claim 4 wherein the control circuitry is configured to produce an output voltage signal based on an offset voltage and charge stored at the floating diffusion node of the non-imaging pixel.
6. An imager comprising,
a pixel array including an imaging pixel configured to produce a reset signal and a non-imaging pixel configured to produce a nominal reset signal, wherein the imaging and non-imaging pixels are configured to be switchably controlled by a common switch signal to output the reset signal and the nominal reset signal, respectively; and
control circuitry operably coupled to the pixel array,
wherein the control circuitry includes an anti-eclipse circuit switchably controlled by the common switch signal, and
wherein the control circuitry is configured to produce an output signal based at least in part on one of (a) the nominal reset signal when distortion at the imaging pixel exceeds a threshold and (b) the reset signal when distortion does not exceed the threshold.
7. The imager of claim 6 , further comprising a sample-and-hold circuit configured to sample and hold a voltage signal corresponding to the nominal reset signal.
8. The imager of claim 6 wherein the non-imaging pixel includes an imaging pixel that is shielded from incident light.
9. The imager of claim 6 wherein each of the imaging and non-imaging pixels includes:
a light sensitive element;
a floating diffusion node; and
a transfer transistor switchably coupling the light-sensitive element to the floating diffusion node.
10. The imager of claim 9 wherein the control circuitry is configured to produce an output voltage signal based on an offset voltage and charge stored at the floating diffusion node of the non-imaging pixel.